MOUNTAIN VIEW, Calif. – Startup SiFive started selling today a $59 Arduino board running its first RISC-V-based SoC and made open source RTL code available online for the chip. The news marks a milestone for a still nascent open source hardware movement.
Open source cores have been available previously but they tended to be academic efforts or lacked broad commercial support. The HiFive board is intended to drive demand for custom SoCs SiFive will design and comes with a growing pool of open source Linux variants and tools fed by an expanding foundation that maintains the RISC-V instruction set.
Demand for open-source chips and the performance metrics for RISC-V SoCs specifically are uncertain, said analysts when SiFive launched in July. The HiFive board will give the market its best chance to date to put both questions to the test.
“RISC-V is really here, anyone can buy and test it,” said Yunsup Lee, co-founder and CTO of SiFive and one of the early leaders in the RISC-V effort.
The startup claims HiFive is the fastest Arduino-compatible board in the market. Its FE310 SoC is a 320 MHz, 32-bit core made in an 180nm TSMC process that is 10x faster and 9x more power efficient than the Intel Curie, also available on an Arduino board.
The SiFive chip delivers 1.61 DMIPs/MHz and 2.73 Coremark/MHz. Compared to other ARM M0 microcontrollers, the FE310 has twice the performance per watt as the average M0 controller, SiFive claims. In raw performance it offers 11x the Drystone MIPS as the Atmel MCU on the Arduino Zero card.
SiFive chose Arduino as its first development board “to enable makers and hackers to work on custom silicon…this is enabling access, it’s a base platform to see what’s possible,” said Jack Kang, vice president of product and business development at SiFive.
The HiFive board includes the open source FE310 SoC. (Image: SiFive)
Most Arduino shields have been ported to the RISC-V instruction set, and HiFive supports the Arduino IDE. “You will see many variations of this platform for other customers or other standards,” Kang said, noting the platform will also accelerate work on software for RISC-V generally.
So far, Microsemi is SiFive’s only public customer, making available in its FPGAs cores from SiFive. Meanwhile, the startup is developing custom silicon for “a small handful” of customers that have not been named.
Separately, SiFive is still working on a 64-bit core supporting cache coherency, targeting data centers and made in a TSMC 28nm process. It is making open source the underlying code for that core so prospective customers can try it out.
The release of the HiFive board is one of the highlights of a workshop here hosted by the RISC-V Foundation. It features talks from commercial members including Google, Micron, Synopsys and a handful of smaller companies. NXP and Huawei recently joined the group and Samsung has publically said it is considering RISC-V as an option for future IoT products.
At the event, Lee will unveil plans for a new foundation to maintain a repository of open source RISC-V products. “That’s part of building an open ecosystem,” he said, noting the products now reside in a repository maintained by the University of California at Berkeley where the RISC-V project began in July 2014.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times