SAN FRANCISCO — Like presents under a Christmas tree, separate papers on 7-nm process technology from TSMC and IBM energized a packed ballroom on the first day of the International Electron Devices Meeting (IEDM). They showed results nudging forward both Moore’s law and extreme ultraviolet lithography (EUV).
TSMC reported the smallest 6T SRAM to date in a process that it aims to put into risk production by April. IBM described the smallest FinFET made to date in a research device made with EUV.
Conference organizers highlighted the papers in October as late-news headliners for the event. Nevertheless, both companies surprised some attendees with more upbeat results than expected.
IBM showed FinFETs with contacted poly pitch of 44/48 nm, a metallization pitch of 36 nm, and a fin pitch of 27 nm. One device included a source-to-drain contact opening of about 10 nm and a gate length of about 15 nm.
TSMC detailed its 7-nm advances over its 16FF+ process (Images: IEDM).
TSMC described a 256-Mbit SRAM test chip with the cell density of 0.027 mm2 with full read/write capabilities down to 0.5 V. The node should provide up to a 40% speed gain, a 65% power reduction, and a 3.3x routed gate density increase compared to TSMC’s 16FF+ process now in volume production, said Michael Shien-Yang Wu, a senior director of N7 development at TSMC.
Although it was not part of his formal paper, Wu also commented on work using the 7-nm process to validate EUV. The next generation lithography provided “comparable patterning fidelity” and “comparable yield” to the conventional immersion steppers it will use in the commercial 7-nm process next year.
The EUV systems from ASML are still in a pre-production release. TSMC already announced its plans to start using EUV in its 5-nm node.
Wu declined to give details of how the 7-nm process compares to its 10-nm node or nodes from rivals such as Samsung. He also declined to give aspect ratios of his 7-nm FinFETs, details about a “novel strain technology” the node uses or figures for yields of a test chip that included a GPU and ARM Cortex A-72 core, except that they were in “double digits.”
The paper gave no indication of what range of voltages that TSMC will support at 7 nm, noted David Kanter, analyst with Real World Technologies. In addition, the paper contained no micrographs which could have revealed whether the node supports air gaps.
Wu did say TSMC had reached 50% yields on its 7nm SRAM. That suggests it is on a path to have volume manufacturing in the process by late 2017, Kanter said.
Next page: IBM details research in patterning, strain
The 7-nm TSMC SRAM hit a new milestone in density.