SAN JOSE, Calif. — Berkeley researchers described a technique that they say cuts the cost and time of making leading-edge chips while creating features smaller than today’s most advanced processes. The so-called tilted ion implantation (TII) process created features as small as 9 nm.
The lab work shows promise for reducing the rapidly increasing cost and complexity of making chips, which has slowed progress in following Moore’s law. However, it’s unclear whether chip makers will adopt the technique.
“We are using argon ions to selectively damage certain parts of a thin masking layer,” said Peng Zheng, lead author of a paper published in the latest issue of the IEEE Transactions on Electron Devices. “It’s self-aligned to pre-existing overlying mask features, so it doesn’t have the issues of [the existing] LELE [method] for which misalignment is a growing issue.”
The approach could cut 50% off the costs of the widely used self-align double patterning (SADP) technique used today at 16 nm and beyond while improving throughput by as much as 35%, he said.
“Implantation is very cheap … compared to SADP, with its multiple layer deposition and etch process,” he said, noting that SADP also requires relatively expensive materials that can withstand processing above 150°C.
The 9-nm feature size in the paper suggests that TII could be used to create 18- to 20-nm pitches. By contrast, TSMC said that its smallest pitches to date are 40 nm for an M0 layer in its 7-nm process described in a paper at the recent IEDM event.
The technique was first described in 2015 to two of the paper’s supporters, Applied Materials and Lam Research. The results of the lab demo were presented at the SPIE Advanced Lithography Conference last year.
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The TII approach created features as small as 9 nm. (Images: Peng Zheng)