SAN FRANCISCO – Engineers need a new class of tools to keep up with the complexity of designing today’s semiconductors, said a keynoter at the International Solid State Circuits Conference (ISSCC) here Monday (Feb. 6). Separate tools need to target today’s four major markets using new techniques and assumptions including machine learning, said Cliff Hou, vice president of R&D at TSMC.
“We need a new design paradigm to overcome chip design challenges,” said Hou. “It’s time for us to evolve our design paradigm, we’ve only covered a small portion of” the design space, he said.
Over the last 10 years the industry has been driven by mobile, building its design databases around smartphone SoCs. “Now we realize mobile is OK as a starting point but we also have to optimize circuits for automotive, high- performance systems and IoT where the considerations are very different,” Hou said, showing four different SRAM designs TSMC uses just for a range of mobile and wearable designs.
Hou’s keynote gave a laundry list of knotty challenges where TSMC is seeing some progress.
For example, resistance at metal layers has doubled between the 40nm and 7nm nodes. TSMC has built up complex stacks of via pillars under wires to significantly reduce but not fully mitigate the issue.
TSMC also is adopting two kinds of metals depending on whether the chip needs greater density or speed. The options “require design changes and EDA enhancements…[and EDA vendors] are aware of this issue and preliminary results look promising,” he reported.
In addition, power networks must be built with greater care to avoid declines in cell utilization as transistor density increases, he said. He sketched out improvements that showed cell utilization rebounding from about 74 percent to 79 percent at 7nm.
“When you design power networks, you have to think of their implications on the design and optimize your layout for it or you won’t get all the advantages of scaling,” he said.
Hou also showed new techniques to handle increasing delay variations as designs move to lower voltage supply levels. In addition, he called for a generation of finer-grained design compilers to optimize for specific area and performance requirements.
Finally, he showed two applications of machine learning to chip design, a hot topic that has recently spawned a new research center. In one application, chip speed increased 40 MHz thanks to models used to predict congestion before routing a chip.
In another example, a leading edge design could generate as many as 20,000 clock gating cells, a group so large engineers would be forced to apply global constraints on them. Hou showed a machine-learning model that could predict latency in the cells and set individual limits on them.
TSMC gained 40 MHz in speed using machine learning to predict congestion before routing a design. (Image: ISSCC)
— Rick Merritt, Silicon Valley Bureau Chief, EE Times