SAN FRANCISCO – Intel gave the most detailed look at its lower cost alternative to 2.5D packaging in a paper on its Stratix X FPGA at the International Solid State Circuits Conference (ISSCC) here. In the same session, AMD showed its Zen x86 processor sports a 10 percent smaller die than Intel’s latest 14nm CPUs.
The Stratix X uses Intel’s Embedded Multi-die Interconnect Bridge (EMIB) to link the FPGA with four external transceivers. The bridge is made using silicon die mounted in a BGA substrate which is significantly smaller than the silicon substrates used in the CoWoS process developed by TSMC and used by rival FPGA vendor Xilinx and GPU designer Nvidia.
EMIB uses a combination of 55 micron micro-bumps and 100+ micron flip-chip bumps to support up to 24 transceiver channels with 96 I/Os each. They deliver 2 Gbits/second/pin at 1.2 pJ/bit/die using a proprietary protocol.
EMIB uses fine-pitch vias and flip-chip interconnects rather than through-hole vias. (Images ISSCC)
Currently, the bridge links four 28 GHz serdes to the FPGA. Intel has a road map to faster serdes and other kinds of external chips, said David Greenhill, an Intel engineer who presented the paper at ISSCC.
The packaging technology drew several questions from a crowded session. Responding to a question from a Xilinx engineer, Greenhill said the Intel team doesn’t foresee any issues dealing with thermal challenges migrating the design to 56G serdes.
Intel announced the technology more than two years ago as an offering in its foundry service. So far, it has not announced any other users of EMIB. The 14nm Stratix X packs 2.8 million logic elements into a 560mm2 fabric running at a gigahertz.
Next page: Zen squeezes x86 area and power
Bridge silicon supports and translates a proprietary EMIB protocol.