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Intel Shows 2.5D FPGA at ISSCC

Zen squeezes x86 area and power
2/7/2017 00:01 AM EST
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rick merritt
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Re: Intel's EMIB approach to 2.5 d integration
rick merritt   2/9/2017 4:42:15 PM
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@chipmonk0  Quite an impressive list!

So, you piqued my interest. When you are ready to give some details, you can find me at rick.merritt@aspencore.com

chipmonk0
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Intel's EMIB approach to 2.5 d integration
chipmonk0   2/8/2017 4:48:00 PM
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is only the latest in a long line of innovations in Adv. Packaging that have been coming out of Phoenix, AZ over the last quarter century and have transformed the industry.

1. Electroplated solder bump flip chip technology ( metallurgy, wafer plating & chip assembly processes ) overall 1/3 as expensive as IBM's earlier C4 process, now the industry standard

2. Computer Vision and Image Processing based Flip Chip Bonding Robot ( 1/2 as expensive as IBM's electro mechanical system ), now the industry standard

3. world first micro - pillar Sn capped flip chip, fine pitch ( 45 um ) & thermo compression bonding tool and process ( now essential to TSV based 3d stacks ), by 1995 robotic line operating at 1,000 uph

4. world first GaAs flip chip used in PAs for Mobile Phones in '96, using above u Pillar flip chip solved both electrical and thermal issues and REDUCED COST over traditonal wire bonded variety, now essential to fast data xfer ( video ) in Smart Phones

5. Organic substrates for flip chip micro processors, proliferation by '99 made possible by new Fabs designed to maintain high yield and reliability even at high volumes ( 2 million units per week ), same design now used by vendors in Far East, application Processors in Smart Phones

6. Sn / SAC capped Copper pillar bumps at 150 um pitch for Micro processors

7. Preliminary research for Wafer Level Packaging

Fabless Co.s up and down CA have benefited GREATLY from above Adv. Packaging technologyies that were originally developed in Phoenix by 2 major IDMs and then recycled via OSATs.

8. Now even OSATs like Amkor and DECA based in Phx are making significant ( theoretically sound thus robust & cost effective ) contributions to next generation of Adv. Packaging.

9. FOLKS IN Si VALLEY INTERESTED IN ADV. PACKAGING FOR HIGH BANDWIDTH DATA TRANSFER BETWEEN PROCESSOR & MEMORY :

WATCH THIS SPACE !!

FOR A LOW COST TECHNOLOGY ALTERNATIVE TO EXPENSIVE TSV BASED STACKED PACKAGING ( which to the cognoscenti is not much better than technology of the Popular Mechanics ilk, easy to dream up and sketch by the dilletanti, hard to realize, hence terribly expensive ).

COMING SOON FROM PHOENIX, AZ TO BOOST SILICON VALLEY UP TO THE NEXT LEVEL OF INTEGRATION

 

 

 

Opteron
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Re: ...
Opteron   2/8/2017 9:48:02 AM
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Two Zen-dies with 8cores wont make any sense. I'd interprete AMD's statement like they taped out one x86 8core (Zen/SummitRidge) and one ARMv8 8core. The K12 project was postponed but is not dead.

realjjj
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Re: ...
realjjj   2/7/2017 7:21:06 PM
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Thanks.

It might be relevant that they mention two designs, both 8 cores with SMT. The assumption is that they would use the same die in both server and desktop.

rick merritt
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Re: ...
rick merritt   2/7/2017 10:34:16 AM
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@realjjj That's what I heard the paper presenter say, and assume he meant the company has taped out two different eight-core Zen chips that are both running at 3.4 GHz.

realjjj
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...
realjjj   2/7/2017 6:36:45 AM
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Sony showed a 3-layers stacked CMOS image sensor (sensor, DRAM and logic). http://www.sony.net/SonyInfo/News/Press/201702/17-013E/index.html

 

Any chance you can clarify this statement: "The company now has two eight-core designs running with simultaneous multithreading at 3.4 GHz."

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