Before all this happened, engineering teams at both NXP and the former Freescale had been already gained substantial experience and knowledge of SOI technology. To them, moving onto FD-SOI is not exactly jumping off a cliff (as it might seem to engineering teams at other companies).
Rather, “FD-SOI is just the latest SOI technology, this time with a design flow almost identical to bulk, but on ultra-thin SOI wafers and some important additional perks like back-biasing,” wrote Ron Martino, vice president of i.MX applications processors and advanced technology adoption at NXP, last year in Advanced Substrate News.
For NXP, the key attraction of FD-SOI technology is the flexibility brought by its back-biasing and forward-biasing techniques. Put simply, “forward back-bias” improves performance, while “reverse back-bias” reduces leakage.
Lees explained, in the IoT space, “We have a really wide range of customers.” He noted, “Some want to operate their device at a really low power all the time, while others want to build a system that can dynamically switch the operating range.”
NXP’s new i.MX7 ULP combines ultra-low power (by dynamically leveraging the FD-SOI’s reverse back biasing) with performance-on-demand architecture (boosted by FD-SOI’s forward back-biasing, when needed). This allows customers to dynamically set an operating range, said Lees.
Moreover, by using FD-SOI dynamic back-biasing, i.MX7 ULP allows different blocks on the chip to be reverse or forward back-biased on the fly to achieve optimal power savings or performance. Specifically, when high levels of processing are not needed, low-power modes kick in with reverse back-biasing of critical subsystems. The ongoing, real-time work is carried on by the smaller, lower powered Cortex-M4.
But when the microprocessor must meet with bursty, high-performance needs such as running Linux or graphical user interfaces, forward back-biasing kicks in.
Previously, such a maneuver was impossible without a more intricate system design that allows an application processor to be turned off or turned down.
The i.MX 7ULP family of processors features NXP's advanced implementation of the ARM Cortex-A7 core, the ARM Cortex-M4 core, as well as a 3D and 2D Graphic Processing Units (GPUs). The i.MX 7ULP family provides up to 32-bit LPDDR2/LPDDR3 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays and camera sensors.
The i.MX 7ULP processor design enables robust low power graphics for the IoT and wearable markets through two graphic processor units (GPU) from Vivante, according to NXP. Those two are: the GC7000 NanoUltra 3D GPU with a low power single shader, and the GC320 Composition Processing Core (CPC) for 2D graphics.
The 3D GPU enables rich 3D based user interfaces, while the CPC can accelerate both rich 3D and simpler 2D user interfaces, said the company. Processors based on the combination of the two GPUs enable efficient display systems which offload and significantly reduce system resources, in turn providing rich user interfaces at low power levels to extend the battery life of devices.
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