PARIS – To do FD-SOI or not to do FD-SOI? NXP Semiconductors’ announcement this week at Embedded World in Nuremberg might finally put an end to this Shakespearean quandary, although there remain players in the chip industry unprepared to face the answer.
NXP launched what the company claims to be the lowest power general-purpose applications processors – dubbed i.MX 7ULP – yet developed for IoT applications.
According to NXP, the i.MX 7ULP design delivers a deep-sleep suspended power consumption of 15 uW or less, 17 times better than its previous low-power i.MX 7 devices. The dynamic power efficiency is improved by 50 percent in the real-time domain.
As previously reported, NXP has been working on microprocessor designs based on fully depleted silicon on insulator (FD-SOI) technology for a while.
The significance of this week’s announcement, however, is that NXP’s senior executive has unveiled a sweeping plan to broadly migrate design and production of general-purpose processors and microcontrollers from CMOS nodes to the FD-SOI process.
In a phone interview with EE Times, Geoff Lees, general manager and senior vice president of microcontrollers, security and connectivity, told us NXP has gained full confidence in the low power, high efficiency and scalability FD-SOI technology can deliver. With FD-SOI, Lees said, “We can now target a variety of family of processors from a single [FD-SOI] process node.”
The microprocessor product lines already transitioning to FD-SOI technology include NXP’s i.MX 7ULP family and the i.MX 8X family for automotive applications. Lees also noted that NXP is “seeing strong interest” in MCU-level products that are also based in this ultra-low power 28FD-SOI technology node. NXP, however, has not finalized launch timeframe with the lead customers or for broad-market introduction.
Not included in the migration plan is the very high-end i.MX 8, designed for advanced graphics and higher performance. The i.MX 8M family – mid-range processors for set-tops and OTT boxes -- would have been a good candidate for FD-SOI, said Lees, but it didn’t migrate because volume orders came before Samsung’s 28nm FD-SOI line was fully qualified.
How it all started
As Lees tells the story, NXP got a call about two years ago from Samsung. The i.MX team was then designing a third-generation processor using Samsung’s 28nm high-k metal gate process. The report from Samsung was that the foundry was seeing “dramatic improvements” in power, performance and efficiency in its FD-SOI process technology.
NXP and Samsung embarked on the development at that time. Samsung’s 28FD-SOI process was fully qualified for manufacture in the spring of 2016, and i.MX 7ULP first silicon arrived in fall of 2016.
The i.MX 7ULP applications processor family is currently sampling to select customers. Broader availability of pre-production samples is scheduled in the third quarter of 2017, according to NXP.
Next page: Why FD-SOI
Before all this happened, engineering teams at both NXP and the former Freescale had been already gained substantial experience and knowledge of SOI technology. To them, moving onto FD-SOI is not exactly jumping off a cliff (as it might seem to engineering teams at other companies).
Rather, “FD-SOI is just the latest SOI technology, this time with a design flow almost identical to bulk, but on ultra-thin SOI wafers and some important additional perks like back-biasing,” wrote Ron Martino, vice president of i.MX applications processors and advanced technology adoption at NXP, last year in Advanced Substrate News.
For NXP, the key attraction of FD-SOI technology is the flexibility brought by its back-biasing and forward-biasing techniques. Put simply, “forward back-bias” improves performance, while “reverse back-bias” reduces leakage.
Lees explained, in the IoT space, “We have a really wide range of customers.” He noted, “Some want to operate their device at a really low power all the time, while others want to build a system that can dynamically switch the operating range.”
NXP’s new i.MX7 ULP combines ultra-low power (by dynamically leveraging the FD-SOI’s reverse back biasing) with performance-on-demand architecture (boosted by FD-SOI’s forward back-biasing, when needed). This allows customers to dynamically set an operating range, said Lees.
Moreover, by using FD-SOI dynamic back-biasing, i.MX7 ULP allows different blocks on the chip to be reverse or forward back-biased on the fly to achieve optimal power savings or performance. Specifically, when high levels of processing are not needed, low-power modes kick in with reverse back-biasing of critical subsystems. The ongoing, real-time work is carried on by the smaller, lower powered Cortex-M4.
But when the microprocessor must meet with bursty, high-performance needs such as running Linux or graphical user interfaces, forward back-biasing kicks in.
Previously, such a maneuver was impossible without a more intricate system design that allows an application processor to be turned off or turned down.
The i.MX 7ULP family of processors features NXP's advanced implementation of the ARM Cortex-A7 core, the ARM Cortex-M4 core, as well as a 3D and 2D Graphic Processing Units (GPUs). The i.MX 7ULP family provides up to 32-bit LPDDR2/LPDDR3 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays and camera sensors.
The i.MX 7ULP processor design enables robust low power graphics for the IoT and wearable markets through two graphic processor units (GPU) from Vivante, according to NXP. Those two are: the GC7000 NanoUltra 3D GPU with a low power single shader, and the GC320 Composition Processing Core (CPC) for 2D graphics.
The 3D GPU enables rich 3D based user interfaces, while the CPC can accelerate both rich 3D and simpler 2D user interfaces, said the company. Processors based on the combination of the two GPUs enable efficient display systems which offload and significantly reduce system resources, in turn providing rich user interfaces at low power levels to extend the battery life of devices.
Next page: Extremely wide dynamic voltage
Extremely wide dynamic voltage
In a very fragmented IoT market where demands from various IoT applications are pulling device vendors into so many directions, the microprocessor’s ability to get an “extremely wide dynamic voltage and performance range” – enabled by FD-SOI – presents a real advantage for i.MX7 ULP.
By showing test chip results of Cortex-Mx performance (see below), NXP claims that i.MX 7ULP takes advantage of 28nm FD-SOI’s unparalleled low power performance. Lees said, “We stand at 7 microAmps/MHz, only 25 percent of what the industry’s absolutely best microprocessor spec offers today -- which is at about 30 to 40 microAmps/MHz.”
Migrating MCUs to FD-SOI
Today, NXP has two MCU lines – Kinetis (ex-Freescale) and LPC (NXP). They are both built on 90nm NVM flash process technologies. The company said that NXP is currently developing next generation families on 40nm flash.
The real time processing domains in NXP’s i.MX 7 & 8 application processors are based on the ARM Cortex M4F processor and IP from the company’s Kinetis MCU roadmap. NXP has developed an "MCUeXpresso" based ecosystem to support application development on these SoCs, according to the company. As a result, NXP is now seeing strong interest in MCU-level products and solutions also based in this ultra-low power 28FD-SOI technology node. Details as to when to deliver solutions for its customers are still being worked out, said the company.
Promise of RF, Non-Volatile Memory integration
The next step for those pursuing the FD-SOI option is the integration of RF and embedded non-volatile memory (eNVM) onto chips.
Lees noted that the integration of eNVM onto high-K metal gate CMOS or FinFET process is known to be “very complex.” In contrast, integrating flash onto FD-SOI is “much more straightforward.”
As for RF integration into the CMOS process, the story gets even tougher for those sticking with it, according to NXP. A growing number of products expected in the IoT space are naturally demanding integration of RF connection, mixed signal and analog. That’s not necessarily the case with the CMOS process, whose evolution is set by massively digital designs.
Unless you are developing “the highest volume” application processors (i.e. smartphones), resources and effort necessary to develop high performance analog for the digital process are hardly justified, he said. “Foundries and chip designers wouldn’t find enough runway” to pull off analog integration.
For the last few decades, the advancement of the CMOS process node has been a yardstick for high-end processors to tout their performance. But that product category (applications processors for smartphones) today is dominated only by a few players.
In the IoT era, the need for diversified microprocessors and microcontrollers takes precedence. More important, processors will compete not just on higher performance, but ultra-low power, efficiency and their ability to integrate RF and eNVM.
Qualcomm’s acquisition of NXP is expected to be final by the end of this year. Will NXP’s FD-SOI roadmap continue under Qualcomm management?
Lees said, “I can’t speak on behalf of Qualcomm.” But he emphasized that NXP has a long-standing strong presence in the embedded market for MCUs and microprocessors.
— Junko Yoshida, Chief International Correspondent, EE Times