SANTA CLARA, Calif. — Trying to cover the waterfront, TSMC disclosed plans for new high-, mid- and low-end processes at an annual event here. They included an enhanced 7nm FinFET node using extreme ultraviolet lithography, a 12nm upgrade of its 16nm process and a 22nm planar technology — its answer to fully depleted silicon-on-insulator (FD-SOI).
The foundry also described enhancements to its two chip-stacking techniques, advances in RF CMOS and work in transistors and materials, paving the way to a 3nm node and beyond. In addition, it previewed design capabilities using machine learning that it will offer before the end of the year.
Among its achievements, TSMC noted 76 percent yields on the 256Mbit SRAM made in its first-generation 7nm node, which will be in volume production next year. It also reported that an ARM Cortex-A72 processor in the node exceeded 4GHz using a new design flow.
The proliferation of different nodes, sub-nodes and platforms threatens to create a dizzying array of options. TSMC has clearly focused on easing migrations for designers, sometimes at the expense of advances measured in single digits.
The Taiwan company, already the world’s largest foundry by far, expects to ship 11 million 12-inch-equivalent wafers this year, a typical 10 percent annual increase. The biggest share—two million wafers—will use its planar 28nm processes for which it is boosting capacity 15 percent this year.
TSMC has taped out nearly 800 chips using flavors of its 28nm process. It has shipped 4.5 million 28nm wafers to date, clearly a big sweet spot it aims to defend.
Globalfoundries hopes to capture many of those customers starting this year with 22nm FD-SOI, a lower cost, lower power alternative with similar performance to TSMC’s 16nm FinFET node. TSMC claims its 22nm process provides an easier migration path from 28nm while FD-SOI requires redesigned intellectual property cores.
“Bulk semiconductor technology has been enhanced for 30 years and is used by Intel and Samsung,” the world’s two largest chip makers, said Mark Liu, TSMC’s co-chief executive in a brief interview after a keynote here. “FD-SOI will always be the technology of the future,” he quipped.
The news comes the same day NXP announced it will use FD-SOI for multiple future processors. So far, a total of just 10,000 FD-SOI wafers/month are shipping from all fabs including Globalfoundries and STMicroelectronics, said Sam Wang, a chip analyst for Gartner.
Globalfoundries may be slightly ahead in timing, ramping its 22nm FD-SOI process now with Sony image sensors in production. TSMC said its 22nm process will be in production next year, aimed at 5G RF and other mobile chips including image processors and components for wearables and the Internet of Things.
The 22nm FD-SOI node sports similar specs to TSMC’s 22nm process, “but it does not have the comprehensive IP ecosystem… and the manufacturing track record we have,” said B.J. Woo, vice president of business development at TSMC.
TSMC also plans an ultra-low power version of its 12nm FinFET process, supporting 0.5V operation and starting risk production before June. It will likely be positioned as a competitor to the 12nm FD-SOI process Globalfoundries announced last year but is not expected in production until 2019.
The ultra-low power TSMC 22nm process should deliver a 20 percent area shrink and either 0.45x the power or 1.32x the speed of its 28 HPM process, Woo said. Compared to its 28 HPC+ process, the 22nm is a direct optical shrink with better transistors and 0.6 Vdd operation offering 10 percent smaller size and 35 percent less power or 15 percent more speed, she said.
TSMC’s 22nm node uses the same mask counts, design rules, SRAM bit cells and I/O devices as its 28HPC+ node. Designers only need to adopt its boosted transistors and re-characterize foundation IP to ensure they meet new margins, Woo said.
“The migration effort is really different [from FD-SOI]—it’s a day and night difference,” said Jack Sun, a vice president of R&D at TSMC.
TSMC’s Liu said the foundry expects 70 tape outs of IoT chips this year across its family of ultra-low power processes that range from 55 to 28nm. The 40nm ULP process has been characterized for near-threshold operation driving energy efficiency to 11 microamps/MHz, he said.
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