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Intel Boots Drives with 3D XPoint

3D XPoint DIMMs already sampling
3/19/2017 12:01 PM EDT
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Ron Neale
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Re: Retention Specs 30 and 40 degrees
Ron Neale   3/29/2017 6:59:10 AM
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Rick and Resistion:- The JES218B-01 spec calls out two data reention times (power off). Enterprise 40C -3months and Client 30C for 1 year. Unless there is a back up with Flash or a DRAM like dynamic rewrite it is difficult to see why active use retention would be different from power off if bits or Bytes are not being written. There is within the spec an active use power on in terms of hours/day, I thought that was separatae from data retention.

resistion
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Re: Doesn't look like SCM
resistion   3/29/2017 12:49:41 AM
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Thanks, Rick, that's the missing information.

rick merritt
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Re: Doesn't look like SCM
rick merritt   3/28/2017 8:21:24 PM
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Finally this response from Intel on the endurance questions below:

"The Intel® Optane™ SSD DC P4800X follows the JESD218B-01 standard for data retention: 3 months of powered off retention at 40C. Powered on, data retention is throughout the product warranty period."

Ron Neale
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Moore's Law-plus scaling-PCM
Ron Neale   3/26/2017 8:04:56 AM
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UBM112211-Intel may well be ahead of the curve, depending on your viewpoint. That is if you consider PCM and (possibly ReRAMs/RRAMs/Memistors) will be the devices of choice for cognitive and learning machines in next generation electronics. Where a single component PCM will be able offer a scaling advantage by the ability to use its unique characteristics as the replacement for multi-component silicon circuits. Offering what might be characterised as Moore's Law-Plus (ML+) scaling. Learning machines and AI may perhaps be a little more tolerant of devices with marginal reliability.

ubm112211
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Re: Yield improvements and cooking CMOS
ubm112211   3/22/2017 10:36:23 PM
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intl is the only comp in the world would spend millions to research sth so far away from mainstream tech. 

hopefully it would pay out.

Ron Neale
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Yield improvements and cooking CMOS
Ron Neale   3/22/2017 1:30:27 PM
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Rick:-Suggesting that the 50% improvement in performance needed for use in DIMMs will be achieved as the yield increases is interesting. This must be interpreted that for the present generation of devices the performance is limited by unknown defect(s) resulting in some devices in all arrays not meeting the intended specification; meaning lower performance arrays are being sampled. Then the performance limiting defects will somehow apparently disappear as a function of increases in yield. Otherwise they would be already delivering at least some arrays with the 50% improvement, more of which will be obtained when the yield improves and a much larger number of arrays meet the same performance level.

Is the problem with CMOS, the matrix isolation device (selector) and temperature related to processing or operation?
The selector devices will be switching on every read cycle as well as the write cycles. Threshold switching is a combination of electronic and thermal effects. If for a particular composition the thermal effect dominates then the CMOS will be cooked during both read and write operations. One intriguing question is have Intel found a threshold switching selector material where the electronic effect dominates or have found one which requires fabrication and post-deposition drift-eliminating annealing temperatures compatible with CMOS fabrication. Some clarification on those points would help judge the likelihood of success.

resistion
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Re: Doesn't look like SCM
resistion   3/22/2017 6:39:46 AM
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Retention, not endurance, thanks.

DataStorage
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Re: 10,000 wpm?
DataStorage   3/22/2017 4:00:08 AM
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"especially the selector diode which needs to work at the low temperatures of a CMOS back-end process." Why low temperature? Does it mean the temperature lower than 300K, OR should it be HIGH temperature?

rick merritt
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Re: Doesn't look like SCM
rick merritt   3/21/2017 11:49:20 AM
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OK, I'm checking woth their PR contact to see if I can get something more specific on endurance.

rick merritt
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Re: 10,000 wpm?
rick merritt   3/21/2017 11:45:19 AM
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Al Fazio noted the Fab 68 in Dalian as one now ramping 3D NAND and implied it could be used for 3DXP if needed, but in my brief talk with him it sounded like they hope 3DXP will fill Lehi fab and Dalian is an option if demand exceeds expectations.

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