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Intel Boots Drives with 3D XPoint

Optane prices debut at 3x NAND SSDs
3/19/2017 12:01 PM EDT
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realjjj
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...
realjjj   3/19/2017 2:55:01 PM
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No overprovisioning yet the drive uses 448GB (28x16) but only 375GB usable...

The pricing is not reasonable nor expected. Last year DRAM was 3$/GB and Xpoint was supposed to be substantially cheaper not 4$/GB. Likely they don't have the production capacity to sell much this year so we'll see where things settle in 2018-2019.

witeken
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Re: ...
witeken   3/19/2017 5:22:05 PM
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Not trying to be personal, but I'm reading a lot negative, imo short sighted comments. Intel has spent probably a ton of money developing this technology, and have yet to see any revenue, so of course the initial costs will be high with low volumes. But of course the costs will fall nicely as this technology matures and the volume goes up with the economies of scale benefits.

Secondly, DRAM progress has basically come to a stand still, while Intel already has 3 generation of 3DXP in the pipline. They can achieve higher bit density and thus cost with three vectors: smalles geometries (and associated scaling beneifts like possibly performance, latency and endurance), more layers (now 2, although not as scalable as 3D NAND), and more bits per cell.

So this technology has a lot of long-term potential. Of course one shouldn't expect a revolution overnight, but this technology is really promising certainly given the general trends in high-performance computing we're seeing.

resistion
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Re: ...XPoint scalability
resistion   3/20/2017 3:15:48 AM
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I would be interested to see the scaling path for 3D XPoint.

The trouble with this version of 3D (as opposed to 3D-NAND) is that adding more layers adds more cost proportionally, so cost/bit saturates. The mature, higher-voltage underlying CMOS should be relatively cheap.

As I understand it is already at the same design rule as DRAM (and in fact NAND) ~20 nm. Whether it can scale lower, could depend on what factors could disturb the cells, e.g., thermal. Also the lines connecting the cells get more resistive, which hinders the reading.

MLC/TLC would be the best or most practical hope. But this requires a mature enough (resistive) memory, and this would also slow down the writing.

The retention is the key for any power savings to be realized. But it is not highlighted, which has me worried for this release..

resistion
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Doesn't look like SCM
resistion   3/20/2017 2:59:48 AM
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A key thing missing here is the storage or retention spec, which should go with any SSD. It doesn't matter how much capacity you have if it disappears while writing.

rick merritt
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Re: Doesn't look like SCM
rick merritt   3/20/2017 11:08:13 AM
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@resistion If you can you be more specific about what retention spec you are looking for, in what units I can see if I can get it.

BTW, good questions on the 3DXP roadmap. However, I am certain they are ones Intel will not answer at this point, though they did say they have the next two generations in development.

elizabethsimon
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Re: Doesn't look like SCM
elizabethsimon   3/20/2017 11:50:27 AM
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The retention spec I'm interested in is how long the data is retained when powered off after being written. I'd prefer numbers in months or years...

If that's not practical, a spec on how long the data is retained when powered up and not refreshed...

As @resistion said, this is critical information to reduce power consumption.

rick merritt
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Re: Doesn't look like SCM
rick merritt   3/21/2017 2:27:45 AM
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@resistion and @elizabethsimon: All the specs Intel is providing are now here:

https://www-ssl.intel.com/content/www/us/en/solid-state-drives/data-center-family.html

Not enough?

resistion
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Re: Doesn't look like SCM
resistion   3/21/2017 3:01:17 AM
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It's not listed, unspecified.

rick merritt
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Re: Doesn't look like SCM
rick merritt   3/21/2017 11:49:20 AM
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OK, I'm checking woth their PR contact to see if I can get something more specific on endurance.

resistion
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Re: Doesn't look like SCM
resistion   3/22/2017 6:39:46 AM
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Retention, not endurance, thanks.

rick merritt
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Re: Doesn't look like SCM
rick merritt   3/28/2017 8:21:24 PM
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Finally this response from Intel on the endurance questions below:

"The Intel® Optane™ SSD DC P4800X follows the JESD218B-01 standard for data retention: 3 months of powered off retention at 40C. Powered on, data retention is throughout the product warranty period."

resistion
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Re: Doesn't look like SCM
resistion   3/29/2017 12:49:41 AM
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Thanks, Rick, that's the missing information.

Ron Neale
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Re: Retention Specs 30 and 40 degrees
Ron Neale   3/29/2017 6:59:10 AM
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Rick and Resistion:- The JES218B-01 spec calls out two data reention times (power off). Enterprise 40C -3months and Client 30C for 1 year. Unless there is a back up with Flash or a DRAM like dynamic rewrite it is difficult to see why active use retention would be different from power off if bits or Bytes are not being written. There is within the spec an active use power on in terms of hours/day, I thought that was separatae from data retention.

resistion
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Re: Doesn't look like SCM
resistion   3/20/2017 12:03:05 PM
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Basically, how long the data is guaranteed at a specified temperature. More impressive if higher than room temperature of course.

geekmaster
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10,000 wpm?
geekmaster   3/20/2017 5:54:03 PM
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Rick! How do you know that "The fab is currently running less than 10,000 3D XPoint wafers/month"? Also: do they also run 3D NAND?

 

rick merritt
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Re: 10,000 wpm?
rick merritt   3/21/2017 2:28:49 AM
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@geekmaster: Al Fazio told me the Lehi fab running 3D NAND is now running single-digit 3DXP wafers

resistion
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Re: 10,000 wpm?
resistion   3/21/2017 9:22:51 AM
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Will they run/ramp this in China Fab 68?

rick merritt
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Re: 10,000 wpm?
rick merritt   3/21/2017 11:45:19 AM
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Al Fazio noted the Fab 68 in Dalian as one now ramping 3D NAND and implied it could be used for 3DXP if needed, but in my brief talk with him it sounded like they hope 3DXP will fill Lehi fab and Dalian is an option if demand exceeds expectations.

DataStorage
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Re: 10,000 wpm?
DataStorage   3/22/2017 4:00:08 AM
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"especially the selector diode which needs to work at the low temperatures of a CMOS back-end process." Why low temperature? Does it mean the temperature lower than 300K, OR should it be HIGH temperature?

Ron Neale
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Yield improvements and cooking CMOS
Ron Neale   3/22/2017 1:30:27 PM
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Rick:-Suggesting that the 50% improvement in performance needed for use in DIMMs will be achieved as the yield increases is interesting. This must be interpreted that for the present generation of devices the performance is limited by unknown defect(s) resulting in some devices in all arrays not meeting the intended specification; meaning lower performance arrays are being sampled. Then the performance limiting defects will somehow apparently disappear as a function of increases in yield. Otherwise they would be already delivering at least some arrays with the 50% improvement, more of which will be obtained when the yield improves and a much larger number of arrays meet the same performance level.

Is the problem with CMOS, the matrix isolation device (selector) and temperature related to processing or operation?
The selector devices will be switching on every read cycle as well as the write cycles. Threshold switching is a combination of electronic and thermal effects. If for a particular composition the thermal effect dominates then the CMOS will be cooked during both read and write operations. One intriguing question is have Intel found a threshold switching selector material where the electronic effect dominates or have found one which requires fabrication and post-deposition drift-eliminating annealing temperatures compatible with CMOS fabrication. Some clarification on those points would help judge the likelihood of success.

ubm112211
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Re: Yield improvements and cooking CMOS
ubm112211   3/22/2017 10:36:23 PM
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intl is the only comp in the world would spend millions to research sth so far away from mainstream tech. 

hopefully it would pay out.

Ron Neale
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Moore's Law-plus scaling-PCM
Ron Neale   3/26/2017 8:04:56 AM
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UBM112211-Intel may well be ahead of the curve, depending on your viewpoint. That is if you consider PCM and (possibly ReRAMs/RRAMs/Memistors) will be the devices of choice for cognitive and learning machines in next generation electronics. Where a single component PCM will be able offer a scaling advantage by the ability to use its unique characteristics as the replacement for multi-component silicon circuits. Offering what might be characterised as Moore's Law-Plus (ML+) scaling. Learning machines and AI may perhaps be a little more tolerant of devices with marginal reliability.

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