The top 10 logic semi companies, plus TSMC all do their own benchmarks as they do early pipeclenaing of their flows for new processes. Be assured that an Apple, QCOM, NVIDIA, MediaTek, HiSilicon, Spreadtrum, or LG will have tried a representative design in at least 2 of the the 3 leading edge processes/IP (TSMC, Samsung, Intel foundry), to pick the best one for their next major SoC. Samsung, Intel, TSMC, and AMD have more commercial limitations on which processes they can try, but they do the same.
No TSMC it is not a loser, but we must to be realistic. The semiconductor market is not growing very fast at all and a day or another (early rather than later) Chinese fouundries will gain a lot of momentum. All this crazy TSMC effort in shrinking at any cost is a bad sign, they want to look better giving few in real performance increase and asking too much for less silicon area. Too bad for TSMC the design rules at finer nodes are very restrictive and the cost in designing a device is growing exponentially. So this push to 7nm or 5nm or 3nm (if ever happen), it will not translate in an industry shift to these nodes. Yes someone will go to, Apple Samsung and few others, still the bulk of industry will stay behind for economic reasons. This huge STOP in silicon shrinking "with economic advantage" will allow to new players to catch up quickly.
It is a bad situation but even with EUV we are at the end of silicon scaling with a clear economic advantage.
So we are reaching the point where controlling the width of silicon features, e.g., fins, is already atomically quantized. The lattice constant of Si is 0.54 nm, so a 10-11 nm fin or nanowire is already atomically forced to suffer at least 10% CD variation from any process.
Not that Intel is interested much in; nearly all its revenue is done manufacturing its own products on the best process for their needs. Yes, a little of foundry could be useful but the bulk of Intel R&D is dedicated to internal products with a reasonable ASP .
Good luck to TSMC to gain real money ion these upcoming crazy dense nodes, i have the suspect 16nm 14nm 12nm will are the sweet spot for many many years from now. Al this talk about 7nm 7nm+ 5nm is stunning, they say many things but nothing about some serious financial advantage. To shrink is easy but what about costs???
I remember you TSMC is only a foundry :). An IDM it's a lot different in needs and investiments. There is another issue, in the medium term a simple foundry is the more sensitive to the China push in silicon tech. A foundry could be dumped quickly by a cheap competitor capable to offer reasonable silicon at lower price just to gain market share. In the long term IDMs like Samsung and Intel are in a far better shape.
Intel's not doing themselves or anyone else a service with a lame FEOL measure of density. Let's get a metric that shows FEOL, BEOL and library tuning for the process. The real measure is how well the process plus the libraries work together across a range of design types performance criteria. Since were dreaming a bit here, I would like to see Intel libraries and process vs. ARM TSMC libraries compared on real synthesiszable designs like a large ARM core complex/SoC and a lage x86 core, targeted at the same clock rates. That's where you would have a chance to see which process was really the densest.