Transistor-density metric proposed
SAN FRANCISCO — Intel will start making 10nm chips this year it claims will lead the industry in transistor density using a metric it challenged rivals to adopt. Separately, it announced a 22nm low-power FinFET node to compete for foundry business with fully depleted silicon-on-insulator (FD-SOI) from rivals such as Globalfoundries.
At 10nm, Intel will pack 100.8 million transistors per square millimeter. It estimated 10nm foundry processes now in production from TSMC and Samsung have about half that density.
Intel’s metric averages density of a small and a large logic cell. Specifically, it uses a two-input NAND cell with two active gates and a scan flip-flop cell with as many as 25 active gates.
“I think it’s a comprehensive, quantitative and honest metric,” said Mark Bohr, a senior fellow and director of process architecture and integration. “TSMC and, I think, Samsung used to quote it, but my guess is they weren’t looking very good with this metric anymore,” he said.
Intel proposed rivals resurrect this density metric to define nodes.Click to enlarge.
The existing metric of multiplying gate pitch and cell height gives a relative advance between nodes, rather than an absolute number of a node’s capability. In addition, it does not include a variety of factors embraced by the density metric Intel proposed, Bohr added.
Whatever the metrics, Intel said it will start making 10nm Cannonlake chips in the second half of this year, three years after it launched its 14nm process. It expects to continue a three-year cadence, stretching 10nm with two annual upgrades to be called 10+ and 10++.
“Even with the longer time between nodes, we’re staying on the same cost per transistor curve and we expect this will continue through the 10nm generation,” said Stacy Smith, executive vice president of Intel’s fab and sales groups.
Interestingly, Intel’s 14++ sports higher performance than its initial 10nm process. However the 10nm node delivers lower power and higher density.
Intel gave more details than usual about its 10nm node. The x86 giant needed to be more forthcoming to show its advantages over 10nm processes already in production at foundry rivals TSMC and Samsung.
Specifically, Intel’s10nm node sports:
- 34nm fin pitches
- 53nm fin heights
- 36nm minimum metal pitches
- 272nm cell heights
- 54nm gate pitches
Intel claimed the node sports the tightest gate and metal pitches in the industry and marks the industry’s first use of self-align quad patterning. FinFETs are 25 percent taller and more closely packed than on its 14nm node.
The company described two transistor innovations to compensate for the rising costs of more lithography patterning steps. A contact-over-active-gate (COAG) helps deliver an additional 10 percent density; a single rather than double dummy gate at 10nm provides additional scaling advantages.
Next page: Praise for 10nm, mixed reactions for metric
Intel claimed its 10nm process is twice as dense as rival nodes. (Images: Intel)
Praise for 10nm, mixed reactions for metric
Analysts were impressed with Intel’s 10nm node, but mixed on whether transistor density was the best metric to gauge competing nodes. It’s too early to tell who will win the significant near-leading-edge business in the increasingly competitive space between 28 and 16nm, they said.
“It’s time to get away from the marketing BS of these node names and let everyone see where the nodes really are…Moore’s law was always about density,” said G. Dan Hutcheson, president of market watcher VLSI Research.
Independent analysts who conduct chip-level teardowns will be able to check density claims using the formula, he said. But a larger size, such as a cm2, would enable a comparison more close to the size of a real SoC, he said.
“We need something to objectively compare the proliferation of node names that show dimensions that are irrelevant to their names,” said Bob Johnson, a research vice president in Gartner’s semiconductor group.
A spokeswoman for TSMC said former metrics based on gate density are better than more recent ones based on cell height.
“That said I have no idea how Intel does its new calculation,” she said. “For example, it's [first-generation 14nm CPU] Broadwell used to have 18.4 million transistors per mm squared, yet under the new measure it suddenly has 37.5 million transistors per mm2. Are they trying to play paper games?”
The TSMC spokeswoman also noted that density alone does not translate directly to die size. Layout and other design rules are all important factors to die size and competitiveness, she said.
Seeing the numbers on the Intel 10nm process, “I was blown away,” analyst Hutcheson said.
David Kanter of the Linley Group agreed. “It's impressive density…but Intel made the point that it doesn’t count until it’s in production,” he said. Nevertheless, “Intel will continue to have a manufacturing lead over everyone else, the question is what that will translate into in terms of products,” he added.
Kanter praised Intel’s COAG transistor advance. However, until the company publishes how it makes COAG devices it will be unclear whether it can use the design as a new way to optimize contact resistance and thus differentiate its processes.
In the new 22FFL space, Hutcheson noted both Globalfoundries and Intel’s foundry group face challenges in developing the wealth of IP rivals such as TSMC have at 28nm.
Next page: FinFETs compete with FD-SOI
Intel provided an unusual amount of detail about its 10nm process.Click to enlarge.
FinFETs compete with FD-SOI
Intel's 22FFL claims cost and power advantages over 28nm planar.
Intel will ramp its 22FFL node before the end of the year, clearly targeting the same kinds of chips for mobile and the Internet of Things as FD-SOI from Globalfoundries and others. A 0.5 PDK is ready now and will be in a version 1.0 by June.
The process includes both high-performance transistors and low power ones with 100x less leakage than their peers in 28nm. It aims to compete with 28nm in costs by using simplified design rules and interconnects while using 14nm-like FinFETs.
“We see it as the easiest-to-use FinFET process in the industry…think of this as FinFET for the masses,” said Smith, until recently, Intel’s chief financial officer.
Specifically, the 22FFL process supports:
- 45nm fin pitches,
- 108nm gate pitches
- 90nm metal pitches using single patterning
- 630nm logic cell heights
- 18.8 million transistors/mm2
- 0.088um2 SRAM bit cell
The gate and metal pitches are significantly relaxed from Intel’s first-generation FinFET 22nm node, which is at 90 and 80nm, respectively.
Bohr showed leakage figures for 22FFL he claimed included sub-threshold, gate oxide and junction leakage. “All three matter,” he said, claiming the node has the “lowest leakage for any mainstream technology.”
Intel declined to provide a specific comparison between 22FL and 22nm FD-SOI. However, it has its own internal products already being designed for 22FL as well as hopes to attract foundry customers.
“Our roadmap going forward will be much, much broader in areas such as IoT and networking…and this enables us to get differentiated performance,” said Murthy Renduchintala, president of Intel’s client and IoT business and systems architecture group.
Globalfoundries' senior vice president of product management, Alain Mutricy, responded to the news of Intel's 22FFL. “Our process is fully qualified for production and we are seeing strong customer demand, with more than 50 active engagements in high-growth areas such as mobile, IoT and automotive,” Mutricy said .
In a blog, Mutricy noted both TSMC and Intel have now announced 22nm processes, two years after Globalfoundries announced its FD-SOI plans. The work “demonstrates the unprecedented innovation that is taking place at advanced nodes that are one or two steps off of the leading edge,” he wrote.
GF’s 22nm process is “fully qualified for production at our Fab 1 facility in Dresden, Germany,” he said. The company “plans to grow the overall [22nm] fab capacity [in Dresden] by 40 percent by 2020,” he added.
In addition, GF announced in February a joint venture fab to make 22nm FD-SOI products in China starting in 2019. It also tipped plans last year for a follow-on 12nm FD-SOI process in Dresden in 2019. “We expect others to follow our 12FDX lead,” he wrote.
For its part, the TSMC 22ULP node “will drive better RF components and it is very competitive in the low power IoT market,” said the TSMC spokeswoman.
Next page: More details in 14nm, foundry
More details on 14nm, foundry
Intel is already planning two 10nm variants, stretching over three years.
Finally, Intel provided more details on its current 14nm process, now in its third variant, 14++. Intel has made three generations of x86 processors in the node as well as its Stratix 10 FPGAs. By the end of the year it will be making its LTE modems in the process, too.
Specifically, the Intel 14nm node uses:
- 42nm Fin pitches
- 52nm interconnect pitches
- 70nm gate pitches
- 399nm cell heights 399nm
- 37.5 million transistors/mm2
- 0.050mm2 SRAM cell
Intel’s use of self-aligned double patterning gives it advantages in tighter pitches at lower cost over other chip makers using litho-etch techniques, said Ruth Brain, a fellow and director of interconnect technology and integration at Intel.
Intel did not announce any new customers for its nascent foundry service. However it did win praise from IP and EDA leaders in a panel at the event led by its foundry executives.
Intel’s custom foundry group “has multiple repeat customers, and you never get that” if you can’t deliver products successfully, said Aart De Geus, chief executive of Synopsys.
The group is “now ready for prime time,” said Will Abbey, a senior vice president of sales and alliances at ARM, which has been working with Intel’s foundry for about 10 months.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times