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ISPD Predicts Chip Futures
4/6/2017

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This year's ISPD contest, sponsored by Xilinx for its FPGA pictured, concentrated on a key constraint in placement, namely clock legalization for reduced runtimes and increased routability as measured by wire length as the primary metric.
(Source: Xilinx)
This year's ISPD contest, sponsored by Xilinx for its FPGA pictured, concentrated on a key constraint in placement, namely clock legalization for reduced runtimes and increased routability as measured by wire length as the primary metric.
(Source: Xilinx)

< Previous   Image 3 of 3   

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