REGISTER | LOGIN
Breaking News
News & Analysis

3D Chip Stacks Eye Data Centers

Oracle project showed shape of things to come
4/12/2017 02:50 PM EDT
8 comments
NO RATINGS
Page 1 / 3 Next >
More Related Links
View Comments: Newest First | Oldest First | Threaded View
chipmonk0
User Rank
Author
Re: Tezzaron ( per Astronut0 ) in TSV and logic chips
chipmonk0   4/13/2017 3:35:35 PM
NO RATINGS
but it is still metal to metal, say the Cu cap on your W filled via to the Cu on an interconnect pad leading to another TSV that could be offset.

the same offset could be done for mainstream Cu filled TSVs too, so its a difference w/o a distinction

the real clear advantage of your technology ( Tezzaron ) is in the use of CVD W to fill the short vias so the CTE compatibility with Si could be exploited w/o getting hit by the higher resistivity of W and also not get stuck w/ the higher expense of creating an order of magnitude taller ( 50 um ) via or having to electroplate Cu into it.

IMHO this whole Cu filled TSV thing got started by certain Fab tool vendors who after selling a few Cu Platers for Dual Damascene at Fab BEOL wanted to create a larger market for their tools.

the thing became a monster fed by Govt research money in Europe and technical naivete / arrogance in Silicon Valley.

( however I too seemed to have played a role in this Popular Mechanics type fantasy since they are using in toto the micro pillar Flip Chip technology that I had developed at Motorola 20+ years ago )

just remember that the main motivation for TSVs in the digital area ( as compared to Sensors & MEMS ) is electrical, there are cheaper ways to skin the cat. 

realjjj
User Rank
CEO
Re: ...
realjjj   4/13/2017 1:43:46 PM
NO RATINGS
The link works fine for me but here's an alternative https://www.google.com/patents/US20160092396

Adding a link for the images associated with the patent, it's a PDF and might take a while to load http://pimg-faiw.uspto.gov/fdd/96/2016/23/009/0.pdf

Interesting that they use the CNL abbreviation so this was aimed at some point at Cannonlake on 10nm.

Astronut0
User Rank
Author
Re: TSV and logic chips
Astronut0   4/13/2017 1:07:56 PM
NO RATINGS
In Tezzaron's 3D stacks the TSVs don't need to line up; in fact, we find it's better if they don't.  The TSV connects to circuitry, not to another TSV.

If I could figure out how to copy/paste a small jpg here...

sw guy
User Rank
Author
Re: TSV and logic chips
sw guy   4/13/2017 10:25:53 AM
NO RATINGS
Thanks

rick merritt
User Rank
Author
Re: TSV and logic chips
rick merritt   4/13/2017 9:55:51 AM
NO RATINGS
@sw guy: Correct

sw guy
User Rank
Author
TSV and logic chips
sw guy   4/13/2017 7:01:28 AM
NO RATINGS
Trying to understand...

I assume TSVs from 2 communicating chips must get same locations.
Hence a new constraint for routing/placement steps,
more easy to solve for memory only chips than for logic ones.

Am I right ?

rick merritt
User Rank
Author
Re: ...
rick merritt   4/12/2017 6:33:18 PM
NO RATINGS
@realjjj

The AMD paper looks like a really interesting extreme use of CPU/GPU chiplets in some kind of 2.5D arrangement with HBM for an exascale super. I'm going to burrow into this more.

The URL for the Intel patent search did not work for me. Can you check it?

Thx

Rick

realjjj
User Rank
CEO
...
realjjj   4/12/2017 4:23:05 PM
NO RATINGS
An Intel patent, more on the topic as they use a smart interposer http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=/netahtml/PTO/srchnum.html&r=1&f=G&l=50&s1=20160092396.PGNR.

A recent AMD presentation at HPCA 2017 http://www.computermachines.org/joe/publications/pdfs/hpca2017_exascale_apu.pdf

 

Most Recent Comments
no clever name
 
betajet
 
pabaines
 
sw guy
 
sw guy
 
resistion
 
emesdoublee
 
Kevin Krewell
 
resistion
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed