SAN JOSE, Calif. — A microprocessor research project cancelled by Oracle gives a glimpse into the future of high-end chip design at a time when traditional scaling is slowing down. The proposed Sparc CPU aimed to use chip-stacking techniques still in development to get advantages increasingly hard to squeeze out of silicon process technologies.
The researcher behind the concept was part of a layoff in Oracle’s hardware group earlier this year. But his ideas live on at a new consulting firm already working with one Silicon Valley semiconductor company.
“The more I look into this, the more I am convinced it is the way to go,” said Don Draper, former senior principal engineer at Oracle who now heads ProPrincipia, a three-person company that he formed.
“Computational density is not growing as fast as internet traffic, and the amount of data for analysis in the data center is growing even faster. To solve this problem, you need more memory bandwidth, and that’s one area where 3D stacking shows its promise.”
In a conference late last year, Draper showed how existing Sparc processors could be redesigned into two smaller, stacked die. One packs just the cores and caches, and another, made in an N-1 or -2 node running at half the data rate, carries peripherals such as serdes, an L4 cache, and on-chip network — reducing costs and power.
Alternatively, the new chips could nearly double the number of cores and L3 cache, especially if the stack adopts emerging microfluidic-cooling techniques. “You can get twice the performance in the same technology node,” said Draper.
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One big CPU can be redesigned into two less costly ones for a mix of cost, power, and performance advantages. Click to enlarge. Images: ProPrincipia.