ANTWERP, Belgium — The semiconductor road map that An Steegen is showing this year has a new node in the upper right hand corner — 14 Å. The placeholder for a 14-angstrom process — a 0.7x shrink from a 2-nm node in 2025 — is a sign of the unflagging optimism of the veteran process technology expert at the Imec research institute.
“We’re still trying to come up with what goes into that bucket, but how we fill it in may be quite different than what we have done before,” said Steegen in an interview at the annual Imec Technology Forum here.
A 14-Å node suggests the atomic limits ahead. A single arsenic atom, one of the larger elements used in semiconductors, measures about 1.2 Å.
As they approach a 14-angstrom future, engineers may start to mix on the same die FinFETs with nanowires or event tunnel FETs or spin-wave transistors. They will certainly start to experiment with more types of memories, and they may be building chips for new kinds of non-Von Neumann computers.
In the near-term, Steegen sees extreme ultraviolet lithography (EUV) being adopted at 7 nm, FinFETs living on to 5- and even 3-nm nodes, and nanowire transistors emerging somewhere along the way.
For now, a 14-angstrom node is just a Powerpoint hope. Click to enlarge. (Images: Imec)
“The confidence level is getting higher and higher from people who work with the hardware” that EUV will be ready for commercial use by early 2020, said Steegen. “Having worked on it for some many years, you see when things are stabilizing.”
Imec was among the first to install prototype EUV systems. It continues to work on one today in its research fab next to a university campus in nearby Leuven.
Steegen expects that EUV “will be sprinkled into process flows at the most critical levels” to make vias and blocks where line ends meet. The work can take three or four passes with today’s immersion steppers, but with its finer resolution, EUV can do it in one.
Engineers working on such advanced nodes will need to check that their designs can be used with either immersion or EUV systems. Those pushing their chips to the reticle limit will use EUV to shrink their designs a bit more.
Despite the small opening, triple and even quad immersion patterning may still be needed to make features with less than a 40-nm pitch. Engineers should not expect design rules to get any simpler anytime soon.
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Imec mapped out the power performance future nodes may deliver. Click to enlarge.