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IBM Claims 5nm Nanosheet Breakthrough

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6/5/2017 09:01 AM EDT
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michgan0
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Re: ....
michgan0   8/6/2017 7:07:13 PM
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Sang Kim


You are telling me that I am posting nonsense or fake news 
as you claim but as you see, at least one EE Times technology 
editor well known has fallen for my misguided ramblings as 
you put it and given them credence. You sound more 
knowledgeable then EE Times technology editor but you are 
not.

Your next question, do you think published electrical 
characteristics from nanowire and nanosheet devices are 
falsified? My answer is No. Not falsified. The electrical 
characteritics all come from nanowires, not from nanosheets 
at all because nanosheets require very large real estates 
compared to nanowires, thus more costly. No nanosheet is 
manufactured just like the nanowires. 

Your next question: "I'm curious: what do you think about 
impact ionization in silicon when the maximum voltage on 
the transistor is 0.7V? "

I provide my answer when you provide the channel or gate 
length and why 0.7V instead of 1V to the gate and drain. 

No semiconductor company can manufacture the nanowire 
transistor today. Therefore, there is nothing to falsify!

Paul1960
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Re: ....
Paul1960   7/7/2017 3:13:57 PM
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in response to michigan0 (or is it Sang Kim?)

Look, you really need to look in the mirror and ask yourself why you're the only person posting this nonsense. It's been going on for a few years now and apparently others, like myself, have tried to ignore you and remain politely quiet. But you are so persistent there's a risk that, like other fake news, an uninformed reader or an analyst might actually believe the stuff you write. I see at least one EE Times technology editor has fallen for your misguided ramblings and given them credence. 

I get it, you once did a project on impact ionization in transistor drains. Do you really think all the transistor engineers in the leading semiconductor companies are oblivious to this possibility? Do you think published electrical characteristics from nanowire and nanosheet devices are fasified? That all the device simulation tools miss this? That $billions are invested in the R&D when there's such an obvious flaw in the device design? Or have you considered there may be reasons why it isn't a problem at these nodes?

I'm curious: What do you think about impact ionization in silicon when the maximum operating voltage on the transistor is 0.7 V?

 

I won't get started here on your other false theme of "Lastly, is such an ultrashort 5nm transistor manufacturable? Depositing such an ultrashort 5nm uniformly and reliably over 12 inch wafers at the manufacturing line is extremely difficult or may not be manufacturable" except to say no one is doing such a thing as you describe (what does depositing an ultrashort 5nm even mean?) and even if they were, uniform 5nm epitaxy is quite manufacturable. 

 

michgan0
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Re: ....
michgan0   7/1/2017 1:05:24 AM
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Sang Kim

First, lets take a close look at the IBM/GF/Samsung
revolutionary 5-nanometer nano sheet transistors.
They are based on the quadruple all-around-gate
technology. For quadruple 7nm test chips with
quadruple all around nano-wire gates claimed by IBM
researchers and its partners are not manufacturable.

For a relatively short conventional linear transistor 
operation or gate and drain are turned on, electron and 
holes are generated at the drain by impact ionization. 
Electrons go to the drain and holes go to the substrate 
with no harm. However, with the quadruple all around 
nano-wire gates promoted by IBM and its alliances when 
hot carriers are generated at the drain, electrons go to 
the drain while holes go to the source instead, resulting 
in the transistor failure. This is because there is no 
substrate for holes to go with the quadruple all around 
nano-wire gates. These phenomena occur with all the 
quadruple all-around nano wire gate transistors 
including the 5nm nanosheet claimed by IBM. This is 
because how 5nm is possible when even 7nm is not 
possible as demonstrated above. Other reasons are: 
5nm channel is so short that the punch-through 
failure occurs and the leakage current due to 
the short channel effects. Therefore, in my opinion the 
5nm nanosheet breakthrough claimed by 
IBM/GF/Samsung is not possible.

Lastly, is such an ultrashort 5nm transistor
manufacturable? Depositing such an ultrashort 5nm
uniformly and reliably over 12 inch wafers at the
manufacturing line is extremely difficult or may not
be manufacturable. If not manufacturable, the 5nm
debate is over.

realjjj
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Re: ....
realjjj   6/6/2017 11:46:51 AM
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Seems too wide ,maybe they are including the nanosheet count so from 1x8nm to 3x16nm.

IanD
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Re: ....
IanD   6/6/2017 11:27:21 AM
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I'm not making any assumption other than the "best" process will probably win...

realjjj
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Re: ....
realjjj   6/6/2017 11:22:54 AM
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Are you assuming that there is no option for fewer than 3 active nanosheets?

IanD
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Re: ....
IanD   6/6/2017 10:18:54 AM
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The "best" process depends on the application and what is most important, just like with current processes. Nanosheets may be good for speed and maximum drive (high performance) but not so good for low capacitance and ability to use small devices (low power consumption).

In many cases nowadays the reason for going to the next node is lower power and/or higher density (smaller cheaper die), and if this drives the processes nanosheets might not be the right answer.

Given the cost of process development (and IP development) it's unlikely that all the process candidates (finFET, nanosheet, vertical nanotubes...) will be successful, the one which is best suited for the biggest part of the market may well push the others into extinction...

R_Colin_Johnson
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Re: ....
R_Colin_Johnson   6/6/2017 9:50:36 AM
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Thanks for the lively discussion on finFETs versus nanosheets at the 5nm node. You guys are the experts--thanks for sharing. When I talk to the engineers in favor or finFETs or nanosheets, they both think their approach is going to force everybody to follow--the way Intel did finFETs first, then everybody followed. But some engineers who are not designing transistors, but just use whichever the foundry offers, think that there may be a variety of architectures offered in the future? Do you guys think there will be a decisive "winner" or a mix of offerings for the advanced nodes beyond 7-nm?

resistion
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Re: ....
resistion   6/6/2017 8:23:19 AM
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That's quite a range but still doable with some form of SAQP.

IanD
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Re: ....
IanD   6/6/2017 6:56:59 AM
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The height of the fin times the number of fins gives the effective channel width; for a wider transistor (higher current) you can either make the fin taller or have more fins.

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