LAKE WALES, Fla. — IBM researchers and their partners have developed a new transistor architecture based on stacked silicon nanosheets that they believe will make FinFETs obsolete at the 5nm node.
The architecture, which was described Monday (June 5) at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan, is the culmination of 10 years of research on nanosheets by IBM, its Research Alliance partners GlobalFoundries and Samsung, and equipment suppliers. Compared to FinFETs, the new architecture consumes far less power, according to the researchers.
The IBM/GlobalFoundries/Samsung revolutionary 5-nanometer nano sheet transistors, with quadruple all-around-gates should give smartphones 2-to-3 day battery life.
The Alliance breakthrough should enable battery powered devices like smartphones and other mobile devices to run for 2-to-3 days on a single charge, as well as boost performance of artificial intelligence (AI), virtual reality and even supercomputers, they say.
Less than two years after developing 7nm test chips with 20 billion transistors, the researchers say they have paved the way for 30 billion transistors on a fingernail-sized chip with quadruple all-around nanowire gates. Test results indicate a 40 percent boost in performance (at the same power as 7nm FinFETs) or up to a 75 percent savings in power compared with today's advanced 10nm transistors.
IBM Research scientist Nicolas Loubet holds a wafer of chips using 5nm silicon nanosheet transistors manufactured using an industry-first process. (Photo Credit: Connie Zhou)
According to IBM, the new 5nm breakthrough to more performance will boost its cognitive computing efforts as well as everybody's efforts toward higher-throughput cloud computing and deep learning, along with lower power and longer battery life for all mobile Internet-of-Things (IoT) devices.
IBM scientists at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY prepare test wafers with 5nm silicon nanosheet transistors to test an industry-first process of building silicon nanosheets. (Photo credit: Connie Zhou)
To achieve the breakthrough the Research Alliance had to overcome the problems plaguing EUV (extreme ultraviolet) lithography, which was already on its roadmap for producing 7nm FinFETs. Beside the shorter wavelength advantage of EUV, the Research Alliance also found ways to continuously adjust the width of its nanosheets in both the chip design and manufacturing process phases. This fine-tuning of performance versus power tradeoffs is impossible for FinFETs, which are constrained by their fin height, rendering them unable to increase current flow for higher performance when scaled to 5nm, according to the researchers.
Science and Engineering’s NanoTech Complex in Albany, NY oversee the operation of the EUV lithography tool used in the industry-first process to build silicon nanosheet transistors that will enable 5 nanometer (nm) chips. (Photo credit: Dan Corliss)
IBM believes its nanosheet architecture will rank alongside proces technoogy breakthrouths in single-cell DRAMs, chemically amplified photoresists, copper interconnects, silicon-on-insulator, strained materials, multi-core processors, immersion lithography, high-k dielectrics, embedded DRAM, 3D chip stacking and air-gap insulators.
Gary Patton, Globalfoundries' chief technology officer and head of worldwide R&D, called the announcement "groundbreaking" and said it demonstrates that Globalfoundries is actively pursuing next-generation technologies at 5nm and beyond.
Also contributing to the Research Alliance's 5nm nanosheets was the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY.
— R. Colin Johnson, Advanced Technology Editor, EE Times