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IBM Claims 5nm Nanosheet Breakthrough

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6/5/2017 09:01 AM EDT
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realjjj
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Re: ....
realjjj   6/6/2017 11:46:51 AM
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Seems too wide ,maybe they are including the nanosheet count so from 1x8nm to 3x16nm.

IanD
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Re: ....
IanD   6/6/2017 11:27:21 AM
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I'm not making any assumption other than the "best" process will probably win...

realjjj
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Re: ....
realjjj   6/6/2017 11:22:54 AM
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Are you assuming that there is no option for fewer than 3 active nanosheets?

IanD
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Re: ....
IanD   6/6/2017 10:18:54 AM
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The "best" process depends on the application and what is most important, just like with current processes. Nanosheets may be good for speed and maximum drive (high performance) but not so good for low capacitance and ability to use small devices (low power consumption).

In many cases nowadays the reason for going to the next node is lower power and/or higher density (smaller cheaper die), and if this drives the processes nanosheets might not be the right answer.

Given the cost of process development (and IP development) it's unlikely that all the process candidates (finFET, nanosheet, vertical nanotubes...) will be successful, the one which is best suited for the biggest part of the market may well push the others into extinction...

R_Colin_Johnson
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Re: ....
R_Colin_Johnson   6/6/2017 9:50:36 AM
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Thanks for the lively discussion on finFETs versus nanosheets at the 5nm node. You guys are the experts--thanks for sharing. When I talk to the engineers in favor or finFETs or nanosheets, they both think their approach is going to force everybody to follow--the way Intel did finFETs first, then everybody followed. But some engineers who are not designing transistors, but just use whichever the foundry offers, think that there may be a variety of architectures offered in the future? Do you guys think there will be a decisive "winner" or a mix of offerings for the advanced nodes beyond 7-nm?

resistion
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Re: ....
resistion   6/6/2017 8:23:19 AM
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That's quite a range but still doable with some form of SAQP.

IanD
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Re: ....
IanD   6/6/2017 6:56:59 AM
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The height of the fin times the number of fins gives the effective channel width; for a wider transistor (higher current) you can either make the fin taller or have more fins.

Violoncelles
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Re: ....
Violoncelles   6/6/2017 6:53:12 AM
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With FINFETs , when you need to increase the width of the transistor , you have to increase the number of fins.

The height of the FIN doesn't control the width of the transistor. Besides , it cannot vary by design , since it is a process parameter.

Violoncelles
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Re: 2-3 day battery life is unlikely
Violoncelles   6/6/2017 6:46:08 AM
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It is a breaktrough .
The structure is completely different from a FINFET.
In a FINFET , the gate controls the channel on only 3 sides.
Here the gates are all around the channels.

In a FINFET , the channel is done in the bulk of the silicium.
Is this the case here ? Is the channel deposited after ? If so how do they make sure that the channel is free from any crystal defect ?

Could you please call Globalfoundries by their name or nickname GF or Glofo.

Not surprising that you deny a breakthrough.

IanD
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Re: ....
IanD   6/6/2017 5:19:02 AM
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For FinFETs increasing effective width means increasing fin height.

The nanosheets are like several stacked fins turned on their side.

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