LAKE WALES, Fla.—Germanium is beginning to replace gallium arsenide (GaAs) for fast radio frequency transistors that are less expensive and also compatible with silicon and CMOS. At the 2017 Symposia on VLSI Technology and Circuits in Japan earlier this month, European research institute Imec presented a pair of papers showing gate-all-around (GAA) transistors that outperform standard CMOS below the 10-nanometer node plus have source/drain contacts with billionth-of-an-ohm resistance.
Imec claims the world's first scaled strained germanium p-channel Gate-All-Around (GAA) FETs with sub-10 nanometer diameter, integrated on a 300-millimeter platform.
The super fast sub-10-nanometer SiGe GAA transistors used strained germanium p-channels on 300 millimeter wafers to demonstrate their superior electrostatic control, achieved by using high-pressure annealing (HPA), which was also demonstrated by Imec as useful for more traditional FinFET architectures.
Setting the new world record in source/drain resistivity at one billionth of an ohm for p-MOS transistor source/drain contacts, the feat was achieved by virtue of shallow gallium implantation and pulsed-laser annealing, according to Imec.
The ability of germanium-on-silicon transistors to perform well as radio frequency transceivers has been well known, since it enables the same CMOS technology used in the rest of a transceiver to avoid the use of GaAs PAs which has an incompatible lattice structure to silicon.
However, at advanced nodes beyond 10nm, it had not yet been demonstrated that SiGe could make the grade for FinFETs or more advanced architectures such as GAA FETs—at least not on a state-of-the-art 300-millimeter wafer. However, using HPA boosted exceptional performance and electrostatic control for both p-channel FinFETs and GAAs, according Imec.
Imec's record breaking 10 billionth of a ohm per square centimeter for p-SiliconGermanium (P-SiGe) source and drain contacts will be shared with CMOS members GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC.
Imec claims that undisclosed architectural changes were able to compensate for the larger permittivity and smaller bandgap of SiGe, making it easier to scale below 10-nanometer without sacrificing electrostatic control. As a result, Imec is claiming the shortest gate lengths (40nm) and the thinnest nanowires (9nm) in the world. The GAA-FETs retained the electrostatic control with a drain-induced barrier lowering of 30mV/V and a sub-threshold slope of 79mV per dec.
Imec also claimed that its HPA technique boosted the performance of both its germanium GAAs and FinFETs. The Imec researchers claimed improved interface quality and hole mobility to 600 cm2/Vs as a result of a HPA at 450°C. Optimizing the HPA significantly improved the electrostatics and overall performance of its GAA devices, reaching a 60 nanometer length and a Q factor of 15 as well as a low current off of 3 to the 10 billionth of an amp per micron.
All the results of Imec's research are shared among its CMOS research members Globalfoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC.
— R. Colin Johnson, Advanced Technology Editor, EE Times