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Gbit MRAM Debuts at Flash Summit

Everspin adds to the persistent memory pool
8/7/2017 08:00 AM EDT
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resistion
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Re: STT MRAM retention time
resistion   8/15/2017 5:12:21 PM
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As Shinobee has pointed out there is a kind of tradeoff between retention and write error (failure to write). The key clue is the MTJ change of state can be thermally assisted or driven directly, similar to PCM, but PCM requires much more energy. So at higher temperature, the change of state is easier to achieve when writing, as well as when not writing.

Shinobee
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Re: STT MRAM retention time
Shinobee   8/9/2017 10:51:47 PM
I guess you are referring to the tradeoff between ease of writing and retention.

 

One way to increase retention time (by making the magnetic material "harder" or "softer" ) is to adjust the ratio of the materials in the MTJ.

For example, TbCoFe / MgO / TbCoFe MTJs can have their retention time adjusted by adjusting the Tb concentration.  Tb exhibits antiferromagnetic coupling, so increasing the Tb concentration will cause the magnetization to become easy to switch, but easier to randomly lose data due to heat.  Doing the opposite will make it more difficult to switch but longer retention.  I'd imagine high level cache memory and SSD would probably lie on opposite sides of that spectrum.

 

(No idea if Everspin actually uses TbCoFe in their MTJs)

resistion
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Re: Fine, but ...
resistion   8/9/2017 8:28:16 AM
The breakdown statistics/distributions different for ultrathin MTJ vs thick ONO.

ip2design
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Re: Fine, but ...
ip2design   8/9/2017 5:23:39 AM
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One point to mention is that the Arrhenius equation (for ageing predicition) is valid for flash memory but not for MRAM. That is why (if we exclude silicon logic), MRAM is supposed to support "unlimited " R/W cycles.

ip2design
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STT MRAM retention time
ip2design   8/9/2017 5:19:56 AM
Everspin MRAM technology is apparently based on STT and retention time is clearly an issue when compared to existing NAND flash. That is why they focus on the cache market. Then,  I wonder how they can address the SSD market without "refreshing" the magnetic cells.

Any idea ?

 

resistion
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Re: Fine, but ...
resistion   8/7/2017 8:39:57 PM
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Both high speed and high retention conditions lead to wear (leading to breakdown) for current-driven MRAM.

sw guy
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Fine, but ...
sw guy   8/7/2017 11:13:32 AM
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I have though for many many years of using FRAM or MRAM as a *safe* cache for a plain old spinning disk.

I assume I was not alone, but flash anyway came to unexpected high, and grab the place.

Next, I wonder how *this* MRAM compare with current flash (and also the coming soon ones) regarding both retention time and wearing
(my understanding is that there is no wearing, hence the ability to use DDR bus, but I am out of my competency area).

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