The resistence-switching mechanism within Crossbar's memory is based on the formation of a filament by the movement of silver ions from the top electrode within amorphous silicon. Source: Crossbar Inc.
Having seen all too many claims about NAND/DRAM replacements over the past 20 years that will be ready for commercialization either next year or the next 2 years or the next 3 years, I have to express amazement that people still get tens of millions of dollars for this. Stan Ovshinsky was the ultimate expert at getting all sorts of companies from Intel to Exxon to give him literally hundreds of millions of dollars over decades for multiple wild projects, very few of which ever resulted any products and even fewer resulted in earnings of any sort. I think ENER might have been that last one and they too went bankrupt.
When someone talks about the magic of the private sector, I either laugh or grimace, depending on my mood at the time.
I think this is still a CBRAM, similar to the one used by Adesto. It relies on diffusing Ag. However, Adesto uses a chalcogenide rather than amorphous silicon. Amorphous silicon is highly temperature sensitive as it is still semiconducting silicon.
Silver too expensive?Not really, when you get down to sub 20nm lithographic dimensions it is more about number of atoms used than the number of ingots. The possible problems with silver are more technical than they are fiscal. Although from a fabrication point of view not much more difficult than introducing copper, now routine.
Those who wish to pursue this silver based memory must first have a firm belief than NAND/NOR will not be able to evolve enough to do the job required of it in the future. The private sector does then give them the opportunity to help underwrite a possible winner. In analogy, the secret of success for those who wish to invest time and/or effort is to separate the signal from the noise.
Against all the potential problems that must be solved the Crossbar memory does appear to offer what I would call a win-win-win situation as an integral part of the memory cell in that it provides: uni-directional matrix isolation, allows the bidirectional current flow required for memory operation and reduces fabrication processing steps.
As somebody who in the past has looked at long carrier lifetime diodes to obtain reverse pulse current flow as well as punch through diodes for matrix isolation to me the Crossbar memory looks worth a development opportunity.
Resistion: I think the difference is the Adesto device is really a solid state electrochemical plating cell, in that ions must be moving in both directions. In the Crossbar memory I am not aware that anything happens other than silver ions move through the a-SiH matrix. Silver is a fast diffuser and in the presence of high field and hydrogen can most likely move easily backwards and forwards through the matrix. The process is perhaps more akin to an electromigration like effect than plating.
A more interesting question is does the filamant actually completely bridge the inter-electrode gap or does it stop short with a tunnelling gap completing the link.
The papers by the developers Sung Hyun Jo and Wei Lu indicated bidirectional switching, rather than using one direction. Ag filaments are formed, though claimed not in the sense of electroplating or "programmable metallization" of the counterelectrode. But even the CBRAM guys have reported unidirectional switching which might be diode-compatible.
But at least for me, it's 'CBRAM' if the source of the filament is one of the electrodes.
The existing technologies aren't that reliable. Sure you have to test reliability with best effort but it's always subject to challenges and customer paranoia. Freescale gets a lot of automotive electronics parts returns from "paranoid" customers. Generates good reliability statistics.
Dr FPGA The technology will stand or fall based on reliability test results. Yes years are needed, but I think very large numbers of devices and memory arrays tested will be a good substitute. The results must be backed up by the exact numbers of devices tested with the exact details of the test conditions under which they were tested and the failure anaysis. The problem is without read verify after every write/erase operation it is possible for devices of this type to undergo write fail-repair cycles with the result that in a free running w/e test the device appears to be operating normally many cycles after a failure would have been recorded in the a real world application. This can lead to erroneous claims of long intrinsic write/erase lifetimes with the problem that those numbers are never achieved with real products. In those cases the definition of intrinsic lifetime appears to be the lifetime achieved once when the claiment was not too careful with the test conditions. Lets hope Crossbar will avoid those pitfalls.