D. Program-Erase Cycling Endurance
Cycling endurance is another attractive feature of CT cell. The widening of cell Vth distribution during cycling is compared in Figure 9, where SMArT cell shows no widening up to 5K distinguished from FG cell having get worse from 3K. This difference is known to be originated from the thin tunneling oxide of CT cell where the interface traps are less generated than FG.
Figure 9: Comparison of Vth widening during EW cycling.
Figure 10: Erase-retention trade-off relationship of SMArT cell.
E. Data Retention
Charge retention is a well known key huddle in CT memory cell, and it is closely related the erase speed. The typical trade-off relationship between the erase speed and the charge loss at high temperature (HT) is shown in Figure 10. The way to reduce HT charge loss without the slow erase is to suppress the conduction of the electron from gate to nitride. The post cycling Vth shift at HT is compared in Fig. 11, where the Vth shift of 3D cell is so large that most margin of the initial narrow Vth distribution is disappeared and finally shows similar Vth distribution of FG.
Figure 11(a). Cell Vth distribution of HT retention after cycling of SMArT Cell
Figure 11(b). Cell Vth distribution of HT retention after cycling of 2y node FG.
Another crucial issue is temperature dependent charge loss mechanism in Figure 12. The Arrhenius plot is not suitable for CT cell, because the nitride loses the stored charge by the band to band tunneling at low temperature (LT) and by thermal emission at HT. Therefore, the lifetime estimated by thermal acceleration as most general in FG cell may not be applicable. It is considered that LT lifetime below 90C could be well evaluated from extrapolation of at least 3-week Vt shift of tail cell, since erratic cell was not found in CT memory .
Figure 12: Temperature dependence of HT retention of SMArT cell.
Future challenges for 3D NAND era
In this section, several important challenges of the 3D NAND flash cell are briefly referred for near future. The first is the total stack height issue. The number of WL stack has to increase consecutively with the progress of 3D technology node, the unit cell size also increases as the stack height to relieve the patterning difficulty of plug and slit etching. However, the large cell size requires more WL stacks again as shown in Figure 13. In order to break out of the vicious cycle, the unit WL stack height has to be scaled down with 3D technology node. This is why challenge of low resistive gate material is so important. In addition, both chip and cell array architecture have to be designed to relax WL loading.
Figure 13: Expected trend of cell area and bit density growth with WL stacks, when cell pitch increases 5% at every technology node.
Figure 14: Trend of cell current and block size as WL stacks.
Second is the decreased cell current issue in Figure 14, where the current is just ~20% of FG even at the first product and then continuously decreases. The low current sensing scheme and the material challenge to enhance the mobility of the poly channel have to be considered concretely. The last issue is the increased block size as shown in Figure 14. NAND controller has to be developed to manage the large block size compatible to every application, and as well as optimized cell array architecture to keep the constant operation stress.
In this paper, the key features of our SMArT scheme which opens 3D NAND flash era are briefly introduced in manufacturability point of view. The device performance and reliability are compared with FG cell of 2y node. The SMArT cell shows the excellent Vth distribution and endurance, while the HT retention is still needed to be improved for highly reliable products. In order to sustain 3D NAND flash era, several challenges such as process, material, and cell architecture have to be overcome to make innovative progresses in near future.
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