Seven intellectual property vendors -- including Andes, ARM, Asocs, Cadence's Xtensa group, Ceva, Imagination's MIPS group, and Synopsys' ARC unit -- announced new comms cores or enhancements to existing cores at the Linley event.
Among the new blocks, Ceva announced its fourth-generation Ceva-XC core. It targets current and next-gen LTE systems. The company claims it's the first floating-point processor DSP for wireless infrastructure. The Ceva-XC delivers up to 40 GFlops and can handle baseband for a 2x2 LTE picocell with as little as 100 milliwatts power.
For its part, Taiwan-based Andes described its N1337 core. Running at rates above a GHz in a 40LP process, it delivers 1.88 DMIPS/MHz and 2.41 Coremark/MHz while consuming 79 milliwatts/MHz.
Separately, Andes unveiled FlashFetch a technique for handling repeated code sequences to reduce power and increase performance on flash-based MCUs using just 9,000 additional gates. For flash running at a quarter the host CPU speed, performance is improved from 54 to 120 percent while cutting power use of the flash in half, the company claims.
ARM used the event to describe enhancements to the Corelink interconnect for creating multicore ARM SoCs. In a keynote at the event, Gwennap said limits in memory bandwidth and pinouts remain the chief bottleneck for comms SoCs.
"When maximum bandwidth is required, we think stacking shows promise, particularly when combined with a new high-speed interface that breaks away from the aging DDR design," Gwennap said in the email exchange. However, "commodity memories will remain the most common due to their low cost," he added.
Freescale leads comms SoCs but has slipped as Intel and Broadcom gain.
(Source: The Linley Group)