SDRAM controller and PHY (Altera)
A DDR4 SDRAM interface
solution provides a flexible method for designers to interface external memory with FPGAs and SoCs. The Altera PHY megafunctions and associated High-Performance Memory Controller II (HPMCII) are two distinct offerings that can be used together or individually. The PHY megafunctions provide the interface between the memory controller and the external memory devices, performing read and write operations to memory. It can be used as part of the HPMCII MegaCore function to create a complete controller and PHY solution for DDR4 SDRAM, or they can be used separately with a custom controller.