When EE Times got back to Pourkeramati about Spansion's interaction with Renesas, he said, "Renesas has not received [a letter from us] yet, but others did."
Without further evidence, it's hard to predict how the flash MCU battle will unfold.
eCT vs eFlash
Two issues that portend some level of conflict are how the two companies' offerings are different and how far have their technologies/product development efforts have progressed.
Tom Hackenberg, principal analyst for embedded processors and automotive semiconductors at the market research firm IHS, told us that the Spansion and Renesas technologies are "very similar," but his firm does "not follow it close enough to comment on whether they are close enough to warrant the current public discussion of patent violations."
They are similar in that "they both involve some similar design improvements over more mature NOR flash technologies typically used in embedded MCUs." Each product "offers a new design with a very thin three layered (insulator, charged plate, insulator) to reduce current leakage (effectively making the whole chip more power efficient), especially when the cell is in the off mode where the charge in the gate is 0V." However, "there are some differences in the cross section of how the gate is structured with Renesas including some split gate design that seems to reduce errors when faults may occur," he said.
The achievements offer similar performance improvements the overall read/write speed and power efficiency for logic ICs that includes embedded NOR flash memory over traditional designs. Both designs are more scalable than traditional designs (mostly because leakage grows rapidly as the technology continues to scale down to physical limits), hence the move to 40 nm further improving speed and power efficiency.
Renesas uses an internally developed memory-cell technology called metal oxide nitride oxide silicon (MONOS) in its eFlash. Each transistor in the flash cell consists of three layers -- oxide, nitride, and oxide -- on a silicon base with a metal gate at the top. Spansion leverages Charge Trap Flash (CTF), which used in the company's own MirrorBit flash memory technology. CTF differs from the conventional floating-gate MOSFET technology in that it uses a silicon nitride film to store electronics. The MirrorBit cell is said to use a charge trapping layer not only as a substitute for a conventional floating gate, but also to take advantage of the non-conducting nature of the charge storage nitride to allow two bits to share the same memory cell.
Fast, low-power split-gate memory cell with cell-select and storage function.
In making their respective technologies more suitable for embedded flash MCUs, both companies have developed new gate structures. Renesas devised a "split-gate structure," which divides the gate into two parts -- one part used as a memory-cell select function and the other for storing data. The select gate is normally off (it's in the OFF state when at 0V), whereas the memory gate is normally on. Spansion used its MirrorBit cell as the foundation for eCT, but it paired a low-voltage select gate to the memory gate of the eCT cell.