The through-chip interface (TCI) compares favorably with today's wired through-silicon vias (TSVs) and traditional chip-to-chip links such as low-power, double-data-rate memory (LPDDR), says the startup.
Yes, the coil impedance losses and required dimensions are nontrivial considerations in the design. On the other hand, TSVs are not a walk in the park either. I think the potential to NOT continually thin the silicon is quite promising. Not to mention the fragility or increased thermal risk, but there is less competitive difference from monolithic approaches.
I wonder about the "potential" for external electromagnetic interference. Slight offsets in positioning might also result in changes of signal amplitude with the risk of digitizing errors. Would it be better to use light communication between the chips (optoisolators)? When encased, there would be no risk of interference, slight offsets or changes in separation would not be an issue, and very high frequency signals could be conveyed without any inductance issues.
Hmmm. It has been many decades since EE school, but if I remember EE101 correctly - you need a change in current on one side to induce a change in voltage on the other side. A SERDES is one way of doing this, but since we have been told (in this article and subsequent comments) that it is a simple circuit to do this, I had to dig deeper.
Then I found a paper in ISCC 2009 titled "Wireless DC Voltage Transmission Using Inductive-
Coupling Channel for Highly-Parallel Wafer-Level Testing".
This paper explains how it can be done. The application in this case was for wafer-test, but the principles are the same.
It is NOT just a matter of silicon cost, but cost at the system level. And even more so, even a 'feasibility' of certain applications. Besides the manufacturing headaches in executing a true 3D structure one is also faced with several others that may be the 'brick wall': yield, thermal, reliability, even FA.