"My concern is on the economic side and whether we are structured in a way to drive through" challenges ahead, said Nick Kepler a veteran process technology expert now a senior advisor to market watcher VLSI Research. Kepler noted a decreasing number of chip makers and the split between foundries and fabless that "splits the motivation to drive toward what you are trying to build."
"There's less choice when there are fewer players and fewer things being explored fully," he said. "Decisions made in research in some cases aren’t the right ones and that gets worked out in the industry but [what] if the industry is not large enough," he asked.
Kibarian of PDF said the chip business is coming down to "a competition of countries." Technology "choices are made very early on -- the payment is huge and if you are wrong, it's huge," he said.
Huang of TSMC argued that while the number of chip makers is decreasing due to industry consolidation, the supporting ecosystems is still strong.
Panelists saw limited potential for the FD SOI technology championed by STMicroelectronics, while two disagreed over the outlook for 450mm wafers.
FD SOI "won't become a significant technology because FinFETs have sucked so much talent and resource out of the industry," said Kepler, a former executive at Globalfoundries which said it will support the process. "Alternatives to FinFETs don't show much of a chance" given the amount of coordinated work among chip designers and makers to deliver process improvements, he said.
"With as much as we have spent on planar transistors, the move to single 3D alternative of FinFETs is amazing to me," Kepler said. The industry consolidation and focus on FinFETs is "good and bad -- it will push FinFETs effectively and exclude other alternatives," he added.
Aitken of ARM said "it's an interesting and open question" whether FD SOI can fill a gap after today's 28nm node where the technology "definitely is a contender." But it runs out of gas before the 10nm where "you can [still] build FinFETs," he said.
"I think 7nm is last standard FinFET node, but you might push it a little," he added.
Brand of Applied noted FD SOI has lower development complexity than FinFETs and an easier, evolutionary road map. However its future also depends on new channel materials that are not mature, he said.
As for a move to 450mm wafers, "a choice has to be made strategically pretty soon if we are going to intercept the point where we need it," said Kepler of VLSI Research. The market watcher said the shift will be needed when Moore's Law slows to doubling the number of transistors in a given area every three or four years.
Brand of Applied said the 450mm shift will come when the industry needs "a round of cost reduction as its primary focus." But the industry, driven by mobile devices, is still focused on lower power today, he said.
Kibarian challenged whether the larger wafers would really provide the lower cost expected. "So much of the process costs is in lithography and when you are scanning twice the area it will take twice as long so the productivity gains will not be there – I don't get it," he said.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times