Transmission electron microscopy shows a 2.7-nanometer channel, sophisticated high-K dielectric, and other advanced features that researchers say make this the world's highest-performing MOSFET. (Source: UCSB)
I tend to agree with your and AKHO's thoughts but would like to add that there has also been a lot learnt over the years in building up the CMOS stable which given the right return on investment scenarios may migrate quicker than the timeline for Si had them do. Ideas tend to find their time based on what else is known and this may prove to be one of them. Not saying you're wrong, just that someone said we would never need more than 640k of memory :-)
AKH0, I agree. We have spent decades working on integrated processes that add all the components to CMOS such as high voltage, non-volitile and DRAM. It will take a long time for the same to happen for this process.
Depends on how you define performance. While the data is promissing, there is no way a device with large parasitic capacitance compete with the state-of-the-art Si. Let alone that none of the III-V devices demonstarted so far as logic replacement are nowhere near Si process in terms of transistor density. Then of course the open question is what is the full CMOS device menu (logic NFET/PFET, memory, and I/O). No co-integration solution has been shown yet.
Good research. This may be good for RF devices, but the question will be at what cost? Will the process be about the same cost as the current production devices? If the cost is the same, it will be implemented.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments