PORTLAND, Ore.—By replicating the functions of neurons, synapses, dendrites and axons in the brain using special-purpose silicon circuitry, IBM claims to have developed the first custom cognitive computing cores that bring together digital spiking neurons with ultra-dense, on-chip, crossbar synapses and event-driven communication.
IBM's effort is the crowning achievement of a "phase zero" and "phase one" contract with the Defense Advanced Research Project Agency (DARPA) to build Systems of Neuromorphic Adaptive Plastic Scalable Electronics (SyNAPSE), IBM and its university partners—Columbia University, Cornell University, and University of California-Merced, and the University of Wisconsin-Madison—now enter "phase two," which extends their efforts for another 18 months with a new infusion of $21 million in funding. DARPA funding the project has received thus far, including the new funding, amounts to $41 million in total.
The eventual goal is to create a brain-like 10 billion neuron, 100 trillion synapse cognitive computer with comparable size and power consumption to the human brain.
"We want to extend and complement the traditional von Neumann computer for realtime uncertain environments," said Dharmendra Modha, project leader for IBM Research. "Cognitive computers must integrate the inputs from multiple sensors in a context dependent fashion in order to close the realtime sensory-motor feedback loop."
Though IBM claims its custom cognitive computing cores are the first of their kind, a rival European program using conventional ARM cores called SpiNNaker— for spiking neural network architecture—was announced last month.
Traditional von Nuemann computers are ill-equipped to deal with the multiple simultaneous data streams coming in from sensors today, but brains handle these easily by distributing processing and memory among its neural networks. In particular, sensors feed neurons down input lines called dendrites.
IBM's Cognitive Computing Chip, at about 3-mm wide, has demonstrated the ability to play (and win) against a human in the game "Pong" and can also read a written letter 7, even when written in various ways.
The neuron integrates over these inputs until a threshold is exceeded, at which point it fires a pulse down its output axon, which is weighted by the synapses connected to other neurons. Pattern recognition is accomplished by the synapses "learning" which connections are used most often, which causes them to grow stronger, while seldom used connections wither away. In this way, the neural network closes the sensory-motor feedback loop, since once a pattern is recognized from the sensor inputs, the output motor neurons mobilize a response.
IBM replicates the brain's architecture by using a crossbar array to hold the synapses, which then learn which sensory patterns correspond to which desired motor control outputs. The crossbar array connects the neurons to sensor inputs by integrating over a large fan-in of dendrites, then firing output pulses down axons which feed individual synaptic connections to the other neurons in the network.
"Synapses are realized with a crossbar array, in which the vertical lines are the input dendrites and horizontal lines are the output axons," said Modha. "Each neuron fires in order to communicate with the other neurons which fully integrates memory with processor, instead of separating them like von Neumann."
Naah, even Apple II's 1Mhz processor could beat humans at "Pong" and read a written letter 7! This is just another scam on the taxpayer, and IBM should be ashamed! The so-called cognitive computer is nothing more than an underpowered curve-fitting device that gets stuck in local extrema, as IBM knows very well. A multi-core CPU with enough DRAM beats IBM's monstrosity in any task, any time.
Mr rbtbob-I am aware, and I tried to cover at least one application of a programmable resistance device, the PCM, in neural applications with the work I reported in:-
Here is my quote from PCM PR#4 that I think is applicable in light of the present stagnant state of commercial PCM product development
“If, going forward, the dreams of neural network emulation are to be fully realized, the challenges to PCM device designers in terms of precision, discrimination and scaling will exceed, by far, anything that has been accomplished to date.”
A quote that is also applicable to all programmable resistance devices, including, CBRAM and ReRAM. Also, with respect, I think you should also be reminded that for the synapse, timing between pre- and post-synaptic pulses as well as conduction change as a function of usage is important.
I can't help but find it a bit odd that IBM is still trying to duplicate probabilistic, over-complete, non-orthogonal, impulse integration systems using perfectly ordered and organized grids of binary devices. Might as well write the whole thing in software at that point. Biological neurons don't send signals in one or two defined routes, rather many directions randomized from neuron to neuron often including back to the neurons that originated the signal. It is interesting to note, though, that their learning algorithm does strengthen or "prune" pathways based on use.
Just to keep things straight, almost all neurons send OUT only one signal along one axon. The axon branches at the end and connects to the dendrites of many other neurons. Neurons may have thousands of dendrites receiving signals from other neurons (or receptors) Axons and synapses are like PCM, there is no possible way they could actually work :-)
PCM brings nothing to the so-called cognitive chip. Even if the cognitive chip made sense (which it does not), its value would be in the connectivity per sq inch (i.e., number of "synapses"), not the storage/counting media.
This is IBM's first generation device, intentionally created to transfer its supercomputer simulations to a hardware platform. As their simulations become more detailed, IBM will have to deal with all the mentioned issues going forward. (And yes, it is relatively easy to program a computer to play Pong or recognize a numeral, which is why these were good metrics for a very simple chip learning a task on its own.)
On reading your explanation of what Stanford had demonstrated, I was amazed that they could perform a resistance change using such a large number of pulses AND, if I understand your analysis, get the device to repeat the cycle enough to demonstrate a workable functionality.
Now the question is whether IBM is pursuing Stanford's scheme or some other? Also, could directional current pulses be used to enable both additive and subtractive resistance changes?