The rest of the industry may need to wait until 2.5-D and 3-D chip stacks are ready for prime time before they can catch up with eDRAM. That won’t happen anytime soon, according to Kevin Zhang, an Intel fellow who lead the eDRAM design and presented a talk on it at the VLSI Symposium.
3-D ICs with through silicon vias “can solve some of the challenging issues facing us like memory bandwidth, but we need to figure out how to do it and lower its cost,” Zhang said, adding it’s not clear when that will happen.
Intel has yet to reveal its plans for chip stacks. Earlier this year Nvidia said it could experiment with them as early as 2014. Micron said it will start shipping this year its Hybrid Memory Cubes, stacks of flash dice with a logic interface.
To craft its eDRAM, Intel created a picoamp-class access transistors, drawing “three orders of magnitude less power than the typical logic transistor,” Zhang said.
Intel used the backend dielectric stack in its 22nm process to design capacitors that store charge while preserving logic performance characteristics. The resulting cells have GHz class performance, leapfrogging the today’s MHz DRAMs. Intel hopes to share more about the data rates it supports in an ISSCC paper next year.
IBM used a very high aspect ratio deep trench at the substrate level to create eDRAM cells it puts on its processor dice. By contrast, Intel uses the dielectric stack, getting results that are both similar and different.
IBM reported late last year a 0.026 mm2 eDRAM cell size, slightly smaller than the 0.029 mm2 size of Intel’s cells. However Intel claims its 17.5Mbits/mm2 arrays are denser than those of IBM. The two companies have similar retention rates, Zhang said.
Intel is shipping products with these eDRAM cells this year. It’s not clear when IBM will ship chips using its latest eDRAM process, Zhang said.
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