To suppress charge loss (Q-loss) between CG and neighbor FG due to lateral high electric field during program, we have adopted an advanced CoSi-based WL air-gap process that has an air-gap portion above 50% between WLs. As shown in Figure 6(a), the electric field between CG and neighbor FG can be reduced 20% by an advanced CoSi-base WL air-gap. However, reduction electric field by WL airgap is not sufficient to prevent charge loss perfectly because of scale-down issues at mid-1x-nm cell size. So N±1 WL bias control scheme were adopted within WL air-gap. As a result we can also reduce the electric field 15% additionally (see figure 6(a)).
Figure 6: (a) Electric field between CG and neighbor FG during programming. (b) 3-D e-field simulation with programmed PV3 neighbor cell. The electric field at point A can be reduced by air-gap and N±1 WL bias control.
Then the advanced air-gap and N±1 WL scheme can greatly alleviate charge loss between CG and neighbor FG by decreasing electric field, as shown in Figure 7. Furthermore, as shown Figure 8, PGM speed is improved by N±1 WL scheme, because FG potential of program cell increase by cross coupling effect between WL and neighbor FG. Figure 9 shows the cell coupling ratio with and without air-gap. Cell coupling ratio can be also improved by air-gap due to reducing capacitance of WL direction.
Figure 7: Improvement of charge loss with N±1 WL bias control method. Charge loss is greatly decreased to ~300mV by applying Vpass+2V to neighbor N±1 WL.
Figure 8: Improvement of PGM speed with N±1 bias control method.
Figure 9: Cell coupling ratio as technology shrinkage.
Read current reduction is also major issue because of higher bulk doping for suppressing short channel effects in mid-1x-nm cell transistors. A new advanced junction scheme of cell and select transistor is adopted to maximize read current and reduce leakage current in unselected block (see figure 10).
Figure 10: Read current with/without select Tr. junction optimization. Read current can be improved by select Tr. junction optimization.
Cell Vth Distribution
Figure 11 shows cell Vth distributions for the multi-level M1X-NAND cells. The Vth distributions have normal shapes and are well separated to three MLC states. This result confirms that M1X-NAND cell technology can be applied for high density MLC.
Figure 11: Three-level programmed Vth distributions of M1X-NAND cells. Vth distributions are well separated to three MLC states.
A highly manufacturable mid-1x-nm NAND flash memory (M1X-NAND) has been developed with new integration technologies, such as QSPT, advanced WL air gap process, floating gate slimming process, and optimized junction formation scheme, to overcome scaling limits of mid-1x-nm technology. The excellent device characteristics and reliability are achieved successfully. And also, a new N±1 WL Vpass scheme during programming has been also adopted to overcome WL-to-WL high field issue. Then, we have demonstrated a middle-1x nm-generation NAND flash memory (M1X-NAND) with high performance and reliability.
1 K. Prall, et al., “25nm 64Gb MLC Technology and Scaling Challenge,” IEEE IEDM Technical Digest
, pp. 102-103, 2010.
2. C. Lee, et al., “A Highly Manufacturable Integration Technology for 27nm a and 3bit/cell NAND Flash Memory,” IEEE IEDM Technical Digest
, pp. 98-101, 2010.
3. H. Shim, et al., “Highly Reliable 26nm 64Gb MLC E2NAND (Embedded -ECC & Enhanced-efficiency Flash Memory with MSP (Memory Signal Processing) Controller,” VLSI Symp. Technical Digest
, pp. 216-217, 2011.
4. K. Lee, et al., “A Highly Manufacturable Integration Technology of 20nm Generation 64Gb Multi-Level NAND Flash Memory,” VLSI Symp. Technical Digest
, pp. 70-71, 2011.
About the authors
This article was contributed by the Flash Device Development & Advanced Process Team, R&D Division, Hynix Semiconductor Inc. The authors include J. Hwang, J. Seo, Y. Lee, S. Park, J. Leem, J. Kim, T. Hong, S. Jeong, K. Lee, H. Heo, H. Lee, P. Jang, K. Park, Myungshik Lee, S. Baik, J. Kim, H. Kkang*, M. Jang*, J. Lee*, G. Cho, J. Lee, B. Lee*, H. Jang, S. Park, J. Kim*, S. Lee, S. Aritome, S. Hong and S. Park
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