At the 44-nm node, Hynix used a saddle-fin transistor as an access device but maintained the old layout of 8F2. The saddle fin scheme is essentially a combination of FinFet and RCAT process-flows. The saddle-fin transistor was designed to decrease storage node write time as well as improve short channel effects with the addition of a partial triple-gate structure. The result is better control over the channel region than the RCAT structure used in Hynix 54-nm SDRAM.
However, it has become increasingly difficult to shrink the cell size using the 8F2 layout. As a result, Hynix eventually adopted the 6F2 layout while also implementing the bWL concept. In the bWL cell, the transistor gates are merged with the metal WL running below the silicon surface level, thus enabling a simple cell structure. Due to a less complex structure, the BL-to-WL capacitive coupling is strongly reduced, resulting in a higher read margin and, subsequently, lower power consumption.
The die is fabricated using a 3x nm CMOS process with stacked capacitor and bWL scheme. Hynix has kept the same WL pitch as that of its previous generation but has reduced the STI spacing by making the active area slanted by 19 degrees from the BL direction as shown in the figure below. The slanted active areas are not continuous but form islands separated by STI. The 6F2 SDRAM unit cell measures 0.131 µm and 0.071 µm along the WL and the BL directions respectively, resulting in a given unit cell area of 0.0093 µm2.
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Figure 2: SDRAM array, at diffusion level, SEM topographical view of Hynix 44 nm (left) and Hynix 31 nm (right). Active areas of Hynix 31-nm device are slanted and the bitline makes a 19 degree angle with the active area.