The three main components of an optimal EM solution are – analysis, prevention and fixing.
signal EM analysis relies on a wide spectrum of data that includes
modeling, extraction, timing, switching activity and foundry EM
constraints/limits. There are two main steps in EM analysis – effective
current calculation and EM violation detection (Fig 5).
current, which includes computing peak, RMS (Root Mean Square) and
average values, helps evaluate the cumulative EM effect on a conductor.
The analysis engine needs to determine these current values for every
routing segment and via in the design. With designs today operating
under different modes and corners, these current values (effective
current and EM limit) will vary based on the timing, voltage and
temperature in every scenario. It is therefore critical to have an EM
analysis engine that is multi-corner, multi-mode (MCMM) aware.
Figure 5: [Components of Signal EM Analysis], Source: Synopsys
effective current values are determined, an EM violation is detected
based on the current limits derived from the foundry EM constraints (Fig
can be implemented for signals that have an increased probability for
EM violation. For instance, due to their high toggle rates and large
drive cells, clock nets are more at risk for EM than data nets. Clock
nets with special width and spacing rules (NDRs) derived from their
driver cells can help minimize the impact of EM. When applied during
clock tree synthesis and honored during route, these NDRs enable a
correct by construction approach to minimize unnecessary perturbation on
the clock nets during signal routing
fixing is a function of sizing wires, vias and cells in order to
effectively reduce the current density through them. A comprehensive
fixing solution much like analysis would also need to be MCMM-aware. Two
commonly used EM fixing approaches are wire widening and cell sizing.
wires help increase allowable current limits and is an effective way to
reduce EM effect. This can be achieved by either applying NDRs on nets
or just by sizing up the violating segments. The latter would be more
suitable to designs that are prone to congestion.
smaller driver cells can help slow down data transition, which in turn
reduces current density and the impact of EM. This method is effective
when there is sufficient timing margin.
to providing a robust MCMM-aware analysis and fixing mechanism, an ideal
solution should have certain key features to facilitate adoption.
Providing seamless integration into a P&R flow would offer easy
setup and quick turnaround time. Not all EM violations are automatically
fixable, hence user control on techniques along with an intuitive GUI
is needed for faster analysis and debug. Lastly, an EM solution within
place and route is effective only when it is accurate and convergent,
making correlation to industry-standard SPICE simulators a must.
IC Compiler EM solution - Ideal for today’s complex designs
Compiler place and route offers an integrated signal EM solution. It
provides comprehensive MCMM-aware analysis and an automated EM fixing
flow. Use of a consistent database provides fast turnaround times, and a
powerful GUI aids analysis and debug of EM violations.
The article clearly needs to emphasize the metric current density vs. current magnitude whether effective, RMS or average values! Temperature effects are of course important but current densities all the way to chip-to-chip (in case of 3D / 2.5D IC) and chip-to-package-level interconnects. Metal lines in IC can take 1E6 Amp/cm^2 current density but interconnects (flipchip or wirebond) and TSV's have lower limits.