Tech execs from ARM, Intel, and Fujitsu did not directly address the issue of latency Barroso raised. However, they agreed that advances in memory and security will reshape tomorrow's computer architectures
John Goodacre, a director in ARM's processor group, showed research in Europe on a microserver based on arrays of 2.5-D chips that put 128 CPUs next to memory on a substrate (below). A separate array of I/O chips will allow I/O and processor technologies to scale independently, he said.
The Euro Server research program is using 2.5-D stacks of CPUs and memory along with separate shared, virtual I/O chips.
Steve Pawlowski, an Intel senior fellow, said new memory architectures on the horizon will give birth to new computing architectures for the datacenter. He shared with ARM's Goodacre the goal of getting memory accesses down to as little as 5 picojoules/byte.
Pawlowski, who is about to take on a new role at Intel heading up security research, called for a quantum leap in work on security. "At some point everything will have to be encrypted, and we will have to have a safe place to save a strong key protected in hardware," he said.
Yasunori Kimura, president of Fujitsu Labs of America, agreed. He showed a technique for accelerating homomorphic encryption by a stunning 2,048-fold using batch encryption and batch encrypted calculations.
Separately, Fujitsu is working on a sensor hub called Sprout to address the rise of data from wearable systems. "Personalized big data is the value of wearables," Kimura said.
He showed two generations of a handheld version of the Sprout hub (below). Ultimately the hub will be integrated in smartphones, he said.
Fujitsu will shrink its Sprout sensor hub to fit into a smartphone.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times