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Ecosystem emerges around new mobile chip tech

Manufacturing, supply chain are key
7/11/2012 04:15 PM EDT
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michigan0
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re: Ecosystem emerges around new mobile chip tech
michigan0   8/31/2012 5:34:50 PM
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It sound like a battle between planer FD SOI by new IBM alliances versus FD Trigate FinFETs by Intel has been declared. The key word here is FD (fully depleted) because both 22-nm transistor for IBM and Intel must be fully depleted to suppress the leakage current or short channel effects. Recently, Leti at the 2011 SOI conference has showed that ultra-thin/un-doped 6nm Si film is required for 22/20nm FDSOI to suppress the leakage current. For the 14nm FDSOI an extremely thin 4nm or less Si film may be required. However, Soitec canít deliver such an ultrathin 6/4nm film in manufacturing. What Soitec can deliver is 12nm Si film and 25nm BOX for 22/20nm nodes. IBM and its alliance members also published FD SOI with 6.5/7 nm Si films at 2012 VLSI Symposium, but these are test chip data, not manufacture-able by Soitec. Meanwhile, for FD finFETs the fin width (W) less than Lg (gate length) or W Lg is only required to suppress the leakage current. It means for 22nm node the fin W can have 21nm or less versus 6nm for FDSOI, and for 14nm node the fin W of 13nm or less versus 4nm for FDSOI. This is enormous advantage for manufacturability of 22/14nm FD finFETs compared with FD SOI. Furthermore, the trigate fins can be doped to adjust Vt, and manufacturability of the tri-gate fins dictates the device scaling. That is why Intel FD FinFETs is in high Volume manufacturing for several months, but FD SOI is not and will not be. The battle is over! S kim

michigan0
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re: Ecosystem emerges around new mobile chip tech
michigan0   8/31/2012 5:45:48 PM
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A little confusion here: W Lg implys that W is less than Lg.

Adele.Hars
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re: Ecosystem emerges around new mobile chip tech
Adele.Hars   12/7/2012 8:44:21 AM
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@michigan. the Leti figure you're citing for FD-SOI Si thickness is *post-processing". The current and next-gen wafers from Soitec et al meet all the requirements. This was explained very clearly by Bruce Doris of IBM a couple years ago, who said (and it is still true), "The top silicon of the starting wafer (currently 12nm) has to be thicker than the final target thickness of the channel since some Si is used up in the process flow prior to final channel thickness definition. " http://www.advancedsubstratenews.com/2010/07/etsoi-substrates-what-we-need/ A lot has happened since you posted this comment -- I think you may find that the battle has just begun...

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