Leti has been working with IBM researchers in Albany, N.Y., and the
French SOI wafer maker Soitec to develop FDSOI technology. The deal with
ST-Ericsson gives the technology a platform for further scaling to 20
nm and lower, the Grenoble-based research institute said.
researchers attribute performance gains to smaller gate lengths at 22 nm
that reduce device parasitics. The resulting performance boost, along
with the use of a technique called back-gate biasing to reduce power
consumption, could provide device makers with “significant
differentiation” in the mobile market, ST’s Magarshack contended.
added that ST is now working with Globalfoundries to “enable the
ecosystem for FDSOI.” Ron Moore of chip IP vendor ARM added that the
next step will be extending the power-consumption benefits of the
process technology to servers and the rest of the mobile infrastructure.
noted that the current infrastructure works out to roughly one server
to deliver content to 600 smartphones. The number of servers needed to
support the millions of new, full-feature smartphones expected to be
sold around the world in the next few years would explode without
significant reductions in power consumption and performance gains, Moore
The partners acknowledged that their competition with
Intel for the next generation of mobile chips comes down to
demonstrating the ability to manufacture chips based on FDSOI technology
while reducing risks in the mobile market for device makers. While
Intel’s FinFET approach is not expected to enter production until the
chip giant rolls out its 14-nm process technology, FDSOI proponents said
they will be ready at 28 nm while continuing to scale to 20 nm.
supply chain will be there,” insisted Horacio Mendez, executive
director of SOI Industry Consortium, adding that it will take six to
nine months to ramp up to full production capacity. “The supply chain
[for FDSOI) is not an issue we need to be worried about,” he claimed.
the ST-Ericsson joint venture, however, the SOI consortium has little
to show so far in the way of customers among device makers. Mendez
conceded that FDSOI performance and power “data is the only thing that
convinces people.” He insisted that the group’s data will eventually
show that it can help manage device makers’ risk in the
hyper-competitive mobile market.
It sound like a battle between planer FD SOI by new IBM alliances versus FD Trigate FinFETs by Intel has been declared. The key word here is FD (fully depleted) because both 22-nm transistor for IBM and Intel must be fully depleted to suppress the leakage current or short channel effects. Recently, Leti at the 2011 SOI conference has showed that ultra-thin/un-doped 6nm Si film is required for 22/20nm FDSOI to suppress the leakage current. For the 14nm FDSOI an extremely thin 4nm or less Si film may be required. However, Soitec can’t deliver such an ultrathin 6/4nm film in manufacturing. What Soitec can deliver is 12nm Si film and 25nm BOX for 22/20nm nodes. IBM and its alliance members also published FD SOI with 6.5/7 nm Si films at 2012 VLSI Symposium, but these are test chip data, not manufacture-able by Soitec.
Meanwhile, for FD finFETs the fin width (W) less than Lg (gate length) or W Lg is only required to suppress the leakage current. It means for 22nm node the fin W can have 21nm or less versus 6nm for FDSOI, and for 14nm node the fin W of 13nm or less versus 4nm for FDSOI. This is enormous advantage for manufacturability of 22/14nm FD finFETs compared with FD SOI. Furthermore, the trigate fins can be doped to adjust Vt, and manufacturability of the tri-gate fins dictates the device scaling. That is why Intel FD FinFETs is in high Volume manufacturing for several months, but FD SOI is not and will not be. The battle is over! S kim
@michigan. the Leti figure you're citing for FD-SOI Si thickness is *post-processing". The current and next-gen wafers from Soitec et al meet all the requirements. This was explained very clearly by Bruce Doris of IBM a couple years ago, who said (and it is still true), "The top silicon of the starting wafer (currently 12nm) has to be thicker than the final target thickness of the channel since some Si is used up in the process flow prior to final channel thickness definition. " http://www.advancedsubstratenews.com/2010/07/etsoi-substrates-what-we-need/ A lot has happened since you posted this comment -- I think you may find that the battle has just begun...
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.