Intel’s component and logic technology development groups in Oregon
“cast a wide net,” exploring available options in processes,
transistors, interconnects, memories and other technologies, “and not
all of them work,” Bohr noted.
Separately, Bohr commented on
Intel’s policy on making chips for other companies. “It’s not our
intention to be in the foundry business, but we do have a small but
growing foundry offering,” he said. Besides selling wafers, the work
provides “a second-order benefit in getting input from other design
teams on how they would like to see our process technology optimized,”
Intel is considering many options including some not on this Intel slide.
In his talk, Bohr said many features in the 22nm process use 80 pitch features, a size chose for this generation because they can be single patterned.
He did not say anything about double patterning at 22nm or quintuple patterning on any process.
I have no doubt that Intel can get to 10 nm with quadruple patterning, but will they be able to suppport a reasonable business model once they get there? And what happens after 10 nm? Is that the end of scaling unless and until EUV litho kicks in at reasonable cost?
Yes, question is not if 10nm can be done but what economic advantage does it bring after spending Billions and Billions of $. With 80nm pitch used for 22nm that would mean ~40nm metal pitch for 10nm. There is no cost effective way to print. Plus even if lithography breakthrough, parasitic capacitance and line resistance are going to be so large chips will be slower and higher power.
Around 10 nm, you cannot merely have a radically new technology come in for one area but a whole package of technologies needed for devices, interconnect, etc. Plus we are now at the scale of electron mean free paths.
Slowed scaling just means that more emphasis has to be put on other aspects of the design. We won't be able to rely on just buying the latest and greatest piece of silicon. Personally I think this is going to be great motivation for better understanding of hardware and the implications of poor coding/software design.
I believe that this is a fairly standard tactic. The process node only identifies the smallest feature that can be reliably resolved and patterned. There shouldn't be any roadblock to making a 90nm sized transistor in 20nm but I'm not a chip designer. Anyone out there that can comment?
For the cost-effective part to make sense, we need the half-pitch or the distance between metal wires to shrink, to enable more transistor connections per unit area. If this distance does not shrink, but only a particular feature shrinks, it could actually add process complexity and some cost.
In theory Intel’s Trigate FinFETs can extend to 10nm beyond as long as lithography can permit because for FinFETs to be fully depleted to suppress the leakage current or short channel effects the fin width (W) less than gate length (Lg) is only required. For 10nm node and below, however, new physical phenomena not seen in wide fin W will occur. The fin W at bottom of the fin for 10nm node and below may approach 6nm or less and 5nm at top of the fin. However, for the fin W with such an extremely thin 6nm may hit the CMOS scaling wall or the end of the Moore’s Law because of the quantum mechanical effects imposed by the structural quantum confinement. It means in simple terms that the electrons within such extremely thin 6nm fin W do not behave like classical particles any more, but instead act as waves. As a result, drift and diffusion based classical semiconductor physics is no longer applicable. Instead, the electron behavior is now described by the quantum mechanical physics based Schrodinger’s wave equations and is subjected to Heisenberg’s uncertainty principle.
The impact of such quantum confinement on the electrical characteristics is a significant increase in threshold voltage Vt due to the mobility degradation caused by decrease in the inversion layer thickness. The Vt increase depends on how thin the fin W is. But this adds to the variation in Vt due to the short channel effect with varying Lg. The other more critical effect is very large variations or uncertainties in transistor transfer characteristics such as Vt, Id/Vg, ID/Vd, DIBL, SS (sub-threshold slop), and SRAM noise. These are physical limits derived from quantum mechanical effects, limiting to the channel length to 10nm node with fin W of 6nm. Process variations not considered here could further adversely impact the variability of finFETs electrical characteristics. Therefore, in my opinion the 10 nm node with fin W 6nm or less will not be manufacturable or the end of CMOS scaling. S Kim
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