For example, SRAM cells won’t get a full 50 percent shrink at 14 nm
without EUV, Ronse said. That’s because multiple patterning has some
limits in how closely it can place features.
“They can only catch
up if EUV becomes available,” Ronse said. “There [are] lot[s] of resources
going into development of light sources, so there is definitely a way to
get there, but it’s hard to estimate if it will be in two years,” he
Intel and TSMC recently committed billions of dollars to ASML (Eindhoven, Netherlands) which is developing the EUV systems.
also recently said it expects to make 14-nm chips next year and could
make 10-nm processors in 2015 using existing immersion lithography.
Without EUV, Intel believes it will have to write as many as five
immersion patterns on a chip which will take more time and money but is
IMEC now gets more than 60 percent of
production time with its ASML NXE 3100 EUV system installed here. “We
had quite some bumpy behavior in the first six months with average up
time declining from 50 to 10 percent,” due to problems with an older
light source, he said.
In its trials, IMEC has achieved device
resolution down to 16-nm half pitch with EUV. “EUV is most likely not
going to be used for all layers [in a chip], but for some critical
layers and will have to be aligned well for immersion,” said Ronse.
is also a problem. To date, IMEC has achieved alignment within 6 nm of
EUV and immersion layers on a chip. It needs to get down to alignment
within 2 to 3 nm, he said.
Something they should have known. So much more energy absorbed from a shorter wavelength photon into a smaller space, obviously higher energy density needs to be dissipated into a larger volume to avoid unwanted material changes.
In one form or another, multiple patterning becomes necessary.
This has been known for years @resistion...I attended IEDM conference 20 years ago where this issue was discussed ;-)...talks about slowing of the Murphy's law started shortly after "the law" was established...I remember limits at 1 micron level considered insurmountable ;-)...but it might be true this time around...litho is clearly a huge challenge...but not the only one...Kris
Wow, that's quite a while back, if I read those papers, maybe I would have reconsidered joining this field, who knows ;-)
I guess saying scaling won't happen would be much riskier than saying a particular way of scaling won't happen.
"Without EUV, Intel believes it will have to write as many as five immersion patterns on a chip which will take more time and money but is still economical." Hope it is true. But when litho rework rate boomed with strigent process requirements in triple and above patterning, process window and yield are impaced severely. It will be hard to see economic advantages in dimension shrinking. It is happening in current 22/20nm processes(double pattern) and getting worse for 14nm and beyond. That is the reason why Intel/Samsung/TSMC(even nVidia) are urging 450mm progress in parallel to lower down process cost. Tons of hurdles ahead, Go engineers.
The EDA enablement of multi-patterning provides a path to maintain a path along Moore's law. The only hesitation has been cost. But what most people are ignoring is the fact that by the time they get an EUV system capable of the numbers they need it will probably cost more than multi-patterning with traditional steppers, and it may even need multi-patterning itself.
would it not be better to make a larger step and go to directed self-assembly (DSA)? multi-patterning feels very incremental with some gains due to smaller feature size and some losses due to lower throughput
DSA is promising but a long road to become production worthy. It becomes more sensitive in Photoresist thickness, temperature and chemical variations. It usually is treated as alternative if EUV or multi patterning fails to meet market requirements.
The dimensional scaling is clearly reaching demising return and escalating challenges. The NV NAND vendor have recognized it and are shifting to monolithic 3D (see Blog piece by Israel Beinglass http://www.monolithic3d.com/2/post/2012/10/3d-nand-opens-the-door-for-monolithic-3d.html)
The logic vendor would sooner or later recognize it too (especially as the would need to carry the burden all by themselves)- the future of scaling is up - monolithic 3D
Monolithic 3D is by far the best way to keep on integration while not increasing the overall power consumption. As for heat removal/thermal consideration, it is not much different than dimensional scaling as the monolithic scaling utilize very thin layers. In fact a detail paper on this issue resulted of a joint work with research group at Stanford university will be presented in the coming IEDM 2012
The advantage of monolithic 3D scaling that we could apply it to an older process yet achieve better benefits than the next node of dimensional scaling. I would expect that the 28nm or 20nm would be a good node to apply monolithic 3D as an alternative to 14nm or 10nm
Isn't monolithic 3D really just an area bump, with some plusses and some minuses? You could in principle also just make chips physically larger in 2-D. A 3-D chip with 2 physical layers is not easier to make than double patterning 1 physical layers, is it? Seems quite similar to a multichip module. My impression is most applications are after higher nodes not because they desperately need more than 10 billion transistors, but that they need better device parameters or cost per transistor.
Lithography is clearly a challenge (and not the only one)and at least it seems that it will need more time.Monolithic 3D with thin layers is an excellent path to continue Moore's Law. There are area that would need engineering such as heat removal and crosstalk but there are no "Red Brick Wall". And as the NAND vendors already adapting monolithic 3D for future scaling, there will be less vendors to support the escalating costs of dimensional scaling for lithography, transistors development etc.
Yes, I agree. Moore's Law is on going and if you look to the original Moore forecast (1965) it is about: " the number of transistors on integrated circuits doubles approximately every two years". Moore attribute it to three trends: Decrease dimension, larger die and improving the architecture. Monolithic 3D is part of the last two. We wrote more about in in our Blog (http://www.monolithic3d.com/2/post/2011/03/guest-contribution-entanglement-squared-by-zvi-or-bach.html)
Just to clarify, Moore's Law was originally:
"The complexity for minimum component costs has increased at a rate of roughly a factor of two per year... Certainly over the short term this rate can be expected to continue, if not to increase."
Stacking die can increase the number of components, but without any significant cost savings I'm aware of. That's not what Moore meant.
Moore's Law has been breaking down now for a decade, in that people like you and me, and practically every other engineer out there, no longer have any meaningful chance of developing a new state of the art chip in the latest process. Only a few remaining giant corporations can afford it, and they apply their fab technology to fewer and fewer high volume chips. The innovation that made Silicon Valley great is no longer being applied to the latest and greatest silicon. In 1988, I laughed at the 1.5 micron three-metal NMOS process used at HP, because everyone was on 1 micron CMOS by then. Anyone even one process node behind was literally a joke. Now days, there are many times more .35 micron tape outs than 28nm. I'm sorry, but Moore's Law is a corpse that is just still twitching...
EUV, unless some fundamental breakthroughs magically appear, will not save Moore's Law.
That said, 3D stacking is cool, and I hope it works out as you envision. There is enormous value in being smaller, if not cheaper.
I strongly agree with your last statement and in fact the strongest value of integrated circuit is being integrated. Integrated function in one device instead of connecting many devices over PC board represent about an order of magnitude improvement in power performance and cost. An important differentiation to be made is between 3D IC using TSV vs. monolithic 3D. While the cost of devices using TSV is not lower but in fact higher the monolithic 3D IC provide cost reduction as we detailed in our Blog (http://www.monolithic3d.com/2/post/2012/06/is-the-cost-reduction-associated-with-scaling-over.html)
You are quite correct, IMHO. EUV would be last on any reasonable scale (had not so many careers not been invested in it) , but DSA wouldn't even be on the scale. Multibeam (a.k.a. e-beam direct write) has been around in various incarnations for decades and always ends up not on silicon, but on masks, where it belongs. Problem is no one will invest solely in mask writers, a tiny, yet demanding market. So, inventors in the direct write space always sell investors on silicon and are invariably disappointed.
EUV is the most expensive to develop, so it requires industrial consortia or collaborations to be able to channel (i.e., waste) this level of spending. I am sure the next thing they will think of is to abandon 13.5 nm and work on the next wavelength 6.7 nm.
I agree with Litho Lady. DSA has made interesting progress and nanoimprint is actually selling multiple tools!
DSA is a another pipedream, the latest shiny penny in a 2 decade search for a replacement for optical when it runs out of gas, which presumably was 2 decades ago. It is yet another screaming example of "nice from far but far from nice". Everyone one of these "solutions" had an Achilles Heel(s) of either source, mask or resist. This includes EUV, a.k.a. soft x-ray projection lithography. Meanwhile, it looks like imprint is indeed on Toshiba's roadmap for nonvolatile memory. Why? Because imprint uses commercial resists, masks, and sources, is cheap, and must only reduce defects.
Airplanes developed at an astonishing rate 1900-1960s. Then 1960s-2012 we pretty much have the same technology in the air.
I see the same thing happening with the semiconductor industry. EUV or Ebeam will be in operation for decades without dramatic improvement in resolution or throughput. The semiconductor industry will not be the highest tech during this future era.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.