ARM showed foils suggesting it could tape out a V8 test processor in 2013 and see customers tape out production 64-bit ARM chips in 2015 and beyond. “We want to co-optimize the process and the processor and solve some of the problems before they come up for our customers,” said Simon Segars, general manager of ARM’s processor and physical IP group in a keynote here.
Segars said TSMC will report more progress on the FinFET collaboration with ARM at ARM Tech Conlater this month.
TSMC’s 20-nm design kits—its first to require double patterning--are available for downloading now. “We made the tools as similar to our 28-nm tools as possible so the double-patterning challenges are minimized,” said Hou.
Chip designers will see changes throughout their designs due to the need for double patterning lithography, and they will be the biggest challenges for coming up to speed with the new node, EDA executives said.
A few companies are taping out their first 20-nm test chips and blocks now, but the process won’t be generally available for use until the first quarter. An analog and mixed-signal designer predicted the 20-nm node will have a long life because designers will not want to move on too quickly to the next node given its requirements for yet another redesign.
Separately, TSMC showed its first 40-nm wafers using 2.5-D stacks where separate die are laid out side-by-side on a substrate. One of the wafers used a 512-bit Wide I/O memory at 200 MHz, sitting next to an SoC and two other DRAMs. Wide I/O is designed for use in 3-D stacks with through silicon vias for products such as mobile apps processors.
The wafers aimed to test out aspects of TSMC’s Chip on Wafer on Substrate (CoWoS) process and the Wide I/O memory blocks. Xilinx is shipping a chip with two FPGA die laid on such a process and made at TSMC, and a handful of other companies have test chips in design using the process.
TSMC currently handles the entire CoWoS process in house, in part because the thinned wafers it requires are too fragile to ship to their party packaging companies. But the foundry is open to working with packaging companies once it finds ways to handle the thin wafers safely, Hou said.
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ARM suggested it will test its V8 design in 16-nm FinFETs next year and see production chips from customers in 2015.
Intel has used double-exposure techniques for its alternating PSM patterning for the poly gate layer starting at 65 nm. Probably multi-patterning on a few layers should be nothing to them now. The question is if they can handle additional layers such as metal 2/3 requiring double patterning.
Double patterning does add a significant amount of complexity to the entire process. And those companies that can do it well will be rewarded. This is where the more vertically integrated companies like Intel and Samsung have an advantage since they can control everything in house. I'm amazed that the foundries like TSMC can execute as well as they do now. But integrating FinFETs, etc. will only make it even more complex to manage in the future. Getting first pass success will become more difficult, and the number of designs at the leading edge will become fewer. Both of these trends are being acclerated by the requirements (costs) of double patterning.
Worse yet, at least some expect 10 nm may require double patterning even for EUV.
And still worse yet, the EUV throughput is still far short of target, so ASML has acquired Cymer. Apparently, they've scuttled their other EUV source vendor options.
Even at 14 nm node, there will be more double patterning layers than multi-patterning layers for sure.
ASML has already said EUV would only be introduced on a few layers, allowing mix-and-match with immersion, but by that time, even the middle layers would be requiring double patterning.
Couple questions about the TSMC 2.5-D Test vehicle you have reported. What was the footprint of the whole thing ( with 4 chips ). Did they give any reason why such a 2.5-D module will be better than current modules / packages used in Smart Phones / Tablets ?
They did not give size of the chip. But Hou did say the test run with Wide IO was only to test out the various aspects of the process and the Wide IO IP which would actually be used with a through silicon via stack in commercial chips.
Couple questions about the TSMC 2.5-D Test vehicle you have reported. What was the footprint of the whole thing ( with 4 chips ). Did they give any reason why such a 2.5-D module will be any better than current modules / packages used in Smart Phones / Tablets ?
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