So, seems the signal thread performance of A57 core will be close to that of Intel Yonah core (Core microarchitecture), and a bit lower than that of Merom core (Core 2 microarchitecture), if SpecInt2000 can be taken linearly, which was designed to.
SpecInt2000 scores (http://www.spec.org/cpu2000/results/cint2000.html):
Core Duo T2600@2.17G = 1796
Core 2 Duo T7400@2.17G = 2284
They were released in 2006 (Jan and Aug?), and TDPs are 31W and 34W respectively.
1250 SPECINT is for a single core Cortex-A57. It's very unlikely you will ever see single-core Cortex-A57 in silicon. CCN-504 will enable 16-core systems. You are comparing single core Cortex-A57 vs dual core Intel. A fairer comparison of what you will see in silicon is 16-core Cortex-A57 vs dual or quad-core Intel. Or compare dual vs dual if you like. But comparing single Cortex-A57 to dual Intel is a silly and pointless comparison.
Some benchmarks in specInt2006 can be auto-parallelized by compiler it has some effect on the overall score.
Not sure about specInt2000 - it was retired long time ago (even specInt2006 was supposed to be retired this year). But it's likely possible to play tricks to make specInt2000 results look better.
It's annoying that ARM uses long retired benchmark. specInt2000 working set sizes are substantially smaller than specInt2006, so just having large cache (which was expensive 5-10 years ago) would give a nice performance boost, e.g. http://cpudb.stanford.edu/visualize/performance_by_freq_and_cache
Based on the VIA report, the SpecInt2000 score of Atom D525 is firstname.lastname@example.orgG, http://www.via.com.tw/en/downloads/whitepapers/processors/NanoX2_whitepaper_201107.pdf.
So, yes, A15 core is able to outperform Atom Pineview core by a nice 40%+ margin. But this performance gain comes with the cost of power. Anand found that, under heavy load, Exynos 5 Dual (A15 core) consumes ~4W additional power over idle, while Atom N570 (similar Pineview core) consumes 2.6W more, http://www.anandtech.com/show/6422/samsung-chromebook-xe303-review-testing-arms-cortex-a15/7.
Atom2 (Silvermont) is supposed to be available in 2013. It will be very interesting to see how does it compare with A15/A57.
Did they go into the bus architecture. Does it use a full AXI bus?
If yes, there is a huge catalog of mature IP that can be put with the cores. If not, well, maybe in version 2.
Also, I have to ask the annoying question, what sort of PMIC will we need to run the thing?
arm is moving really fast. we have caught it with arm9, arm11, arm cortext a8, a9, but now it moves to A50!
yet each arm platform find it way on different usage.
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Power aside don't forget ARM parts are made for switch and MP blades and dense implementations.
Four nodes per blade at 16 cores on the work load places ARM 32 bit parts while memory limited, and certainly any 64 bit part, in Xeon DP/MP performance territory. Benchmark the compute module not the individual processor. Mike Bruzzone at Camp Marketing
I won't judge the ARM performance until the real product exist. Just 1 years ago, there are full of people in EETIMES argued that "based on benchmark" the ARM a9 was 2~4 time faster than current atom, and were soon busted by the comparison between real mobile product. Don't take me wrong, I don't mean those people are incapable, but the result from ARM is just misleading and bluffing. They also declared the ATOM is incapable of being used in smartphone until 22nm when then medfield was already in massive production, what a reputation.
Medfield is already highly competitive with the best ARM's licensees can field and that's on Intel's older 32nm LP process;
Silvermont is a fundamentally new ATOM microrachitecture on a new 22nm LP process and it's been tweaked to the last femtoferrad by the Intel Army.
The combined Haswell and Silvermont Intel avalanche is coming in 2013 and I can't wait to see how the market/competition respond!
Re slide 7:
- irrespective of whether the compiler can auto-parallelize the SpecInt code, if the benchmark includes stuff that probes how well the cores can access shared data, that 'stuff' needs to be optimized to the target hardware.
- the slide horizontal axis is labelled 'threads', with an implication that each thread is running on a dedicated core.
- the figures given for the A57 indicate that 4 cores give about 3 times the performance of a single core..
- this could be indicative of a potential issue of excessive latency in the interconnect that links cores to memory etc..
Re performance: claimed vs realized: @wsw1982, the marketing guys will always try and claim the biggest figure they think that they can get away with; but behind the scenes, the engineers BETTER have an EDA environment that allows them to run the actual benchmark code on a simulation of a complete test chip (albeit rather slowly...); so they know the reality already (within the simulation environment accuracy limits.... eg DDR response time modelling...). If they don't have this capability, some people may get some 'surprises' when they start to evaluate the real Si...