Bohr said it was now abundantly clear that 22-nm tri-gate SoCs outperformed 32-nm planar devices by a margin of 20 to 65 percent, while covering four different orders of magnitude in current leakage.
Intel said its 22-nm tri-gate product also exhibits superior short channel control, with optimum sub-threshold slope and drain-induced barrier lowering (DIBL). The sub-threshold slope allows for low leakage but could also function well at low voltage, making them “much better than the very best planar devices," Bohr added.
Bohr said the low numbers for DIBL seen in testing were a measure of good performance in short channel control, with the new SoC pulling in DIBL numbers of 30 to 35mVs, while comparable products had DIBL’s closer to the 100mV range.
Bohr said that when Intel had first announced it would be using tri-gate devices, other companies had argued that FinFET transistors would not aid analog design. “Well, they’re wrong,” declared Bohr.
For analog designers, he asserted, an important transistor metric is trans-conductance by power out (GM x Rout). Bohr said that while this value had been steadily degrading over the past few generations, it had shot up again in 22-nm trigate SoCs, making it easier for analog circuit designers to use than Intel’s previous three generations of planar technology.
Bohr also touted the technology's advanced passive features, including precision resistors, MIM capacitors and high Q inductors.
This looks like (at least) a dual gate oxide SoC, so it's definitely more expensive to make than single gate oxide logic. Triple gate oxide is not unheard of either. The gate layer in this case is therefore already triple patterned for non-lithographic, electrical reasons alone.
Everyone who plays/played the "Master of Orion" or the "Civilization" series of global/galactic strategy games knows that "raping the tech tree" is the key to victory. I can't see how that's any different for the semiconductor industry and the process technology tree.
TSMC has an infrastructure and process to enable IP houses to develop analog, memory and other process-specific IP. That way anyone who uses the new process can choose from many offering. That's my understanding why Intel's mobile offerings are so poor-featured compared ARM-based developed by Qualcomm, Samsung and Nvidia. Tri-gate process is a great improvement and the step in the right direction to enable mobile market, but I am not sure if this is sufficient alone. Even if Intel opens its fab to others today, it still has a lot to catch up with the way other fabs are supporting their customers. Thanks for the interesting article!
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.