Intel jump started the FinFET approach with its new 22-nm tri-gate process, but it is not delivering on its promise, asserted an IBM process technology expert. Intel’s Ivy Bridge chips made in the process deliver just 20 percent power reductions compared to 35 percent drops with the former node, said Ghavam Sahidi, a fellow at IBM Research.
“The real numbers are not very impressive, IBM got much better numbers and Intel’s own 45- and 65-nm numbers were better,” he claimed.
Sahidi blamed parasitics that resulted from Intel’s decision to dope the FinFET structures. “If they go down this path to 14 and 10 nm of doping, it gets worse--you have to be un-doped,” Sahidi said.
Thompson of SuVolta agreed. “I think Intel went down a path of un-doped fins, but I think they couldn’t solve their problems, so they went into production with doped fins and sloped horribly,” Thompson claimed. “I think that structure will not give the power or performance people expect and the right thing to do is an un-doped fin,” he said.
Intel will need un-doped FinFETs to support multiple threshold voltages needed for the analog circuits key to mobile SoCs, Thompson said. He predicted Intel might try such a move at its 14-nm node.
Thompson suggested only high performance processors and FPGAs will need FinFETs. The growing class of mobile chips will be served by planar 28 nm or older processes. “We are leaving a big chunk of market behind,” he said.
Others disagreed. “FinFETs will last a long time, and I certainly expect the next generation to be better than the current one,” said Chenming Hu, a professor at the University of California at Berkeley and a former chief technologist at TSMC. “I would not say FinFETs will go to the end [of CMOS scaling] because a better way is to think of using many building blocks--it doesn’t have to be one."
3 big customers have committed to making foundry planar 20nm next volume node versus pick 20nm finFET (called "14 or 16nm")
Rest still deciding. There is no meaningful data anywhere on foundry Finfet so perhaps they have the same problem as Intel.
IBM's left hand does not seem to know what the right hand is doing - the foundry manufacturing landscape appears in complete disarry - poor UMC "sucker" - no wait UMC figured out long before IBM that SiLK though it looked great on paper could be manufactured...
UMC licenses IBM technology for 20-nm FinFETs
www.eetimes.com › News and Analysis
Jun 29, 2012 – (UMC) has licensed technology from IBM Corp. to expedite the development of its 20-nm CMOS process, including FinFET 3-D transistors, the ...
I want to go with FD-SOI because when the substrate is fully depleted meaning no doping(theoretically) and hence the substrate will have very high resistance.
This means that the drain and source of MOS transistors can be very close as ST-Micro suggested less than 10nm (8 , 5 , ..) and still gate will have good control over the drain current which is crucial for MOS transitors to work properly.
FD-SOI will not be completely new step like Intel's 3D stacked MOS transistor architecture.
Hence FD-SOI will be more cost effective in terms of material cost of MOS transistor manufacture.
Digital MOS : FD-SOI , 3D or carbon wires will be good.
Analog MOS : ????? (for less than 10nm)
Carbon wires will be a boon for digital chips of the future with more than 10 billion switches on chip. may be good for memory as well like processor caches and SRAM kind.
Are you backing FinFETs? FD-SOI? Gemanium? Tunnel FETs? and why?
Why is AMD abandon SOI after using it for years?
AMD will therefore move on from SOI based processes next year. Kaveri that will replace Trinity will be made with 28 nanometer technology, which CTO (Chief Technology Office) Mark Papermaster confirms will be Bulk-based. The same year the cheap and energy efficient platforms Kabini and Temash will arrive, which will build on a similar 28 nanometer technology. There were not details on who will supply the process, but most likely Kaveri will be made by GlobalFoundries, while TSMC will produce Temash and Kabini.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.