“Electrical signaling is not necessarily dead after 25G,” says Adam Healey, a systems architect at LSI Corp., referring to one of three papers he co-authored for DesignCon 2013.
The paper reports on a simulation Healey helped conduct showing 40G and even faster interfaces may be viable given existing and advanced serdes and signal integrity techniques. “If you assume reasonable silicon scaling, you can get healthy looking eyes at these higher speeds,” said Healey, another veteran of the event.
That opens the door for cost- and space-reduced versions of today’s four-lane, 40G Ethernet products collapsed into a single lane. It also points the way to new interfaces such as 64G Fibre Channel even though the 32G version is still being hammered out.
The faster speeds will require more sophisticated modulation techniques such as four-level pulse amplitude modulation. The hyper-efficient PAM-4 is already being written into the draft 100GBaseKP4 standard for running 100G signals over today’s 10G backplanes, Healey said.
No one has implemented such sophisticated signaling yet, Healey said, but it’s coming. “At 10G, people didn’t need it; at 25G some people want it; and going to 40G and beyond…” you may have to give it a spin despite the trade-off of lower immunity to noise, he said.
Meanwhile, a gradual transition is clearly ahead. Engineers working on brand new designs that they want to last for awhile might consider this a good time to explore use of optical channels
“A lot of technologies being considered for on-chip and chip-to-chip optics are relatively new with unknown cost and risk factors, but they deliver a clear path for bandwidth scalability,” Healey said. “Each OEM will have to make some tough decisions on a case-by-case basis about what they use,” he added.
DesignCon 2013 papers co-authored by Adam Healey:
Equalization in high-speed serial systems
Statistical analysis of serdes