Chip makers must move to the “very complex” process of double patterning with immersion lithography starting at 20 nm, Patton said. But IBM has worked on ways to hide much of that complexity under either a standard cell design flow or for more advanced users a custom flow based on a relatively simple algorithm he added.
An electron with 1.5 eV kinetic energy has 1 nm wavelength. If we keep on reducing voltages and dimensions we could have some quantum crossover, like at ~2 nm. If the dimensions are (already) less than the electron mean free path, then it gets really interesting.
I think that is the reason for the interest in silicon photonics. A group at Northwestern has made a bow-tie shaped 3D metamaterial nanocavity with a negative index of refraction and demonstrated a laser that defies the diffraction limit of light, emitting coherent IR wavelength light from a cavity structure that is much smaller than the wavelength. This shouldn't be possible either, but it is.
Sometimes we think we know, based on the best available science, only to find out later that the science wasn't quite right. Nano-photonics is at this stage, just now finding oddities in optical principles that have been considered sacrosanct since the 19th century.
If photonic chips can be built with the same CMOS process, and it looks like they can, then I think we will be using photons instead of electrons before 2 nm is reached. Yet there remains the possibility that the as of yet untested predictions are not quite accurate, so we won't know for certain where the quantum limit is until we can actually reach it and the theoretical physics versus experimental physics debates are settled.
These subwavelength optical confinement activities are related to plasmons. The surface plasmon polariton modes in metamaterials is the source of negative refraction. But plasmons have their own well-known limits.
It seems a bit early to be predicting what will happen at 7 nm, but if DSA continues to rapidly evolve then perhaps it can be a disruptive technology by then. If we are stuck with quad patterning I can't see it being cost effective.
Patterning at 7nm is obviously tough but sounds people think it can be done...but is Mosfet still working at 7nm?...what is Ion/Ioff ratio?...how many dopant atoms are within transistor volume? what about statistical variations that could be huge?
That is the length of the whole unit cell. There are more atoms within the cell since it is a diamond crystal structure. Actual figures depend on orientation but for a 100 direction it would be 4x that.
IBM has been mostly irrelevant to semiconductor process technology for at least a decade. I doubt many outside IBM can clear state why they even still do it. They certainly don't make any money from it. Yerning for the glory days perhaps?
IBM Makes its money from Selling Enterprise Systems, that include full bundle including Software, Servers, data warehouse, and services. IBM Chip tech is developed for its server Chips and related SOCs, That gives them tech advantage over competition.
HS seems to have an understanding of why IBM is still in semiconductors, mainly to support their systems business, and in that regard they are successful. It is a relatively small operation with one 200 mm and one 300 mm fab - running about 5 process nodes worth of tech under one roof v. Intel's many Fab high volume operation, why even make a comparison there ? Two different businesses. I am not a Phd like I imagine many of you commentators are, so can you please explain why you consider the gate first approach to be so inferior v. gate last ?
I have seen both Gate 1st and gate last processes, what really matters is whether each tech can provide the published specs with reasonable yield, in time for customer shipment. Non-Intel fabs have had a hard time delivering Yield on time in HKMG ,primarily coz,it was their 1st time producing it in 32/28nm. Intel was already playing with it since 65nm days.,
There are two competitive semiconductor technologies today: FD-FinFETs by Intel and FDSOI by IBM. Major difference is scalability. Based on the semiconductor device physics theory, the FDSOI channel thickness required to suppress transistor leakage current is 7nm for 22nm-node, 4nm for 14nm-node, 3nm for 10nm-node, and 2nm for 7nm-node. Meanwhile, for FD-FinFETs the fin width (equivalent to channel thickness) required is 22nm for 22nm-node, 14nm for 14nm-node, 10nm for 10nm-node, and 7nm for 7nm-node or fin width = gate length, Lg. What a large difference favoring FinFETs! For the 22nm-node FDSOI the channel thickness of 7nm is required while for 22nm FinFETs the fin width as large as 22nm is required to suppress transistor leakage current. That is why Intelís 22nm FinFETs are in high Volume manufacturing for almost two years, and 14nm will be manufactured at 2014, but FDSOI at 22nm and below will not be manufacturable because Soitec canít deliver such thin 7nm, 4nm, 3nm and 2nm FDSOI. What Soitec can deliver today is high volume manufacturing of 28nm SOI wafers with minimum 12nm SOI and 25nm buried oxide. FinFETs are not dependent on Soitec wafers.
IBM Patton predicts the next big thing after FinFETs will be carbon nanotubes. But he doesnít say at what technology node FinFETs will end? Intel Mark Bohr said FinFETs can be extended to the end of scaling. I disagree with Mark. In my opinion it is plausible to manufacture the fin width equal to 7nm, but not below because of the quantum confinement induced device variability. The manufacturability of the 7nm carbon nanotube with possibly 3nm or less nanotube diameter has not been demonstrated yet. The other critical issues are self-heating, source/drain resistance and quantum confinement effects. Skim
The Rayleigh resolution limit (k1=0.61) of ASML's EUV tool (NA=0.33) is 25 nm. So by the time they use for 7 nm, it would need the same OPC and enhancement tricks used for 193 nm immersion today. But EUV was originally justified as a way to avoid these tricks. In that sense, it has already failed its promise.