The road to chip stacks is still fraught with difficulties, especially for packaging houses. When looking at costs and yields of 3-D chip stacks, “my biggest concern is the supply chain by far,” said David McCann, vice president of packaging R&D at Globalfoundries.
Most foundries plan to ship wafers with TSVs to packaging companies such as Amkor, ASE and others. The packagers will bond a silicon or glass carrier wafer to the active wafer, thin the active wafer to expose the TSVs then remove the carrier wafer. “That process is slow, tools are expensive and yields are erratic,” said McCann.
“The yield of the bonding and especially the de-bonding is very, very poor and I haven’t heard a solution for it yet,” said Herb Reiter, president of EDA2ASIC Consulting Inc. (Los Gatos, Calif.).
In addition, suppliers still need to slice tens of percentage points off the costs of the packaging process as well as the job of making the TSVs and the memory chips themselves, McCann said. “We have to drive each of those to critical price of implementation—it’s not exactly clear what those critical prices are, but we have to drive down all three,” he said.
“The cost pressure on smartphones is so high that 3-D ICs at the beginning will have a hard time to find sockets there,” Reiter said. But cost and space pressures are less extreme in tablets that could be a home for simpler 2.5-D techniques, he added.
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Globalfoundries aims to work with third-party packaging firms on 3-D ICs.