It will be revolution by evolution as the new software and new hardware emerge in a chicken-and-egg dance.
The current 1.x versions of OpenFlow represent a compromise. “Ideally we would have started it as a generic match-and-action flow, but it had to be mapped on to existing chips—the next generation will be more protocol independent,” McKeown said.
Last year, the Open Networking Foundation (ONF) that oversees OpenFlow engaged ASIC makers in a so-called Forwarding Abstractions working group. It aimed to narrow the gulf between what OpenFlow wants to enable and what existing and planned ASIC do.
Now ONF is starting a new effort it calls a chip advisory board. “We will learn from them what’s possible [in silicon], and out of that will emerge what’s possible for the next generation of OpenFlow,” he said
OpenFlow began using content-addressable memories as an intermediary to interface to router and switch ASICs, but the approach limited its functionality. More recently it has used a technique of matching multiple tables.
“The protocol independent version [of OpenFlow] will take awhile,” McKeown said.
Why not a hybrid chip that is predominantly "off the shelf" coupled with a good sized very fast internal FPGA?
The issue with a prediction such as this is not only do you have to predict where performance of merchant chips will go, but also predict where the future of networking may go. We can make assumptions about bit growth, but are all our other assumptions going to be right?
Well duh, I say :-) . What took so long? One only has to look at the history of the computer to see the exact same thing happening circa 1980. When a certain large semi chip supplier sold off their industry leading network processor business a few years ago I thought (and purely expressed the view ) that it was a very shortsighted move for the very same reasons. Time will tell whether Cisco is the DEC of the past 20 years.
"When a certain large semi chip supplier sold off their industry leading network processor business a few years ago"
If you are talking about Intel selling off Xscale, I heard that it was underpowered and power-hungry, (and difficult to program) and thus not really competitive with other chips on the market.
It was also based off of ARM processors. Intel may regret giving up ARM processor experience, but I think their network processor needed some work.
That's not fully correct. The IXP1200 (and I believe its predecessors), featured an ARM processor for control plane processing along with 6 microengine processors specialized for packet processing.
Still... this is interesting that it's coming up again.
I think that as CPUs become faster and faster, there is a very logical trend to do more in software and less in hardware. So this can be applied to IP routers as well.
My problem is mostly with hyping this up as "reinventing" anything. Much like software defined radio, what it does mostly to to increase flexibility and upgradeability. But it doesn't reinvent anything at all.
The question is not just "will ASICs be replaced in com gear" but "will ASICs be replaced (in everything)". I believe the writing is on the wall for ASICs. They are on the way out, squeezed from both ends by ASSPs and FPGAs. In ten years the ASIC industry will be a shadow of what it is today.
By the way, in today's high priced com gear most of the heavy lifting is done by FPGAs anyway. Yes, the high level software control still goes through the ASICs, but it is the FPGAs that push the packets forward to their destination.
I am sure that ASICs will be around for a long time (longer than we expect anyway), but the trend has been away from full custom ASICs towards FPGAs/programmables for some time now. The cost in time and money to develop full custom ASICs has been the impetus for many designs to switch to FPGAs. Given the improved performance/cost/size of the current FPGA families with on die processors I would only expect this trend to continue. With the development of software defined networking and the time for it to mature it makes a logical next step. I wonder how many companies will be left behind..?
nick should take a look at xelerated dataflow architecture which was created in 2000 - that solves the packet processing excatly like he is suggesting with a very deep pipeline of classify action blocks and has fully programmable dataflow processor element which gives hundred percent deterministic behaviour
so the new breed of network processors that nick wrote a paper on has been around for 13 years
xelerated was bought by marvell for a few years ago and is still til this date the only programmable npu that is deterministic by design
Was the xelerated architecture talking about a completely protocol independent chip design ? Nick is talking about In-
silicon implementation of forwarding abstractions that has a general applicability to any type of communications forwarding problem.
A company called Spider Systems used to make network hardware (routers, bridges, terminal servers and SNMP probes) based on the Intel 386 and 960 processors back in the 1990's. Cisco then moved to custom ASIC's and RFC protocols. I have a couple of Squiggle magazines from this time.
You left a key leader in software defined networks off of your list....BROCADE COMMUNICATIONS. Brocade is using a combination of ASICs, FPGAs and high-performance network processors in many of their current products and has paved the way for SDNs ahead of our competitors!
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.