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Exclusive: TSMC plots microelectronics future

5/13/2013 08:04 PM EDT
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resistion
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re: Exclusive: TSMC plots microelectronics future
resistion   5/13/2013 11:16:41 PM
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So tsmc locked with Mapper or still evaluating REBL and others?

R_Colin_Johnson
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re: Exclusive: TSMC plots microelectronics future
R_Colin_Johnson   5/14/2013 2:00:33 AM
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No, TSMC is still evaluating ASML and KLA Tencor as well.

resistion
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re: Exclusive: TSMC plots microelectronics future
resistion   5/14/2013 7:35:49 PM
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Ok thanks. I doubt industry likes sole sourcing a new technology, though.

double-o-nothing
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re: Exclusive: TSMC plots microelectronics future
double-o-nothing   5/15/2013 1:21:56 AM
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But remember the positive charging.

chipmonk0
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re: Exclusive: TSMC plots microelectronics future
chipmonk0   5/14/2013 5:23:14 PM
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TSMC is right in finally accepting that there is a long way to go in terms of design methodology yield improvement etc. before they can hope to use 3D die stacking for jelly - bean like Smart Phones. Since they seem to be putting a lot of their competitive eggs ( vis a vis Intel ? ) into the basket of stacking dissimilar dice by 3D, wish the EE Times reporter had quizzed them on specifics and not let them get away with "motherhood" type statements. Oh well !

docdivakar
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re: Exclusive: TSMC plots microelectronics future
docdivakar   5/20/2013 3:14:10 PM
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Few topic come to mind if there is a follow up to this article with TSMC: -what is TSMC's plan to bring the costs down in 3D IC integration? -why isn't TSMC actively promoting / nurturing ecosystem partners that can perhaps develop cost-effective technologies (such as interposers, cooling technologies, etc) than organic efforts? -is there a product vision / road map for heterogeneous integration? MP Divakar

the_floating_ gate
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re: Exclusive: TSMC plots microelectronics future
the_floating_ gate   5/14/2013 6:22:04 PM
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Chipmonk - you posted this back in November and you were right on the money. 3D is too costly for low priced SoCs "Haswell is going to be a 2.5 d module with the Level 4 cache chip next to the processor, the chips connected by fine-pitch high-density thin film interconnects on the Si substrate of the module. Will have lots of interconnects, enabling lots of parallelism in memory accesss by multi - core in CPU / SoC. BTW won't be able to stack chips ( true 3D ) because need to take heat out of the 10 watt CPU."

alex_m1
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re: Exclusive: TSMC plots microelectronics future
alex_m1   5/17/2013 12:55:15 AM
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Since intel use 2.5 integration , which means they can mix and match tech, I wonder why did they used expensive edram instead of cheap commodity dram ?

Chipguy1
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re: Exclusive: TSMC plots microelectronics future
Chipguy1   5/14/2013 9:21:28 PM
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Sure 10nm can be done with ebeam....but at what cost is the right question. Not cost effective for mainstream SOC. moores law roadmap is becomming clearer. 28nm is lowest cost per transistor and where bulk of cost sensitive SOC made

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