However, just as important as advanced node CMOS, according to Sun, is using 3-D to tie these advanced chips together with all the other analog and mixed-signal capabilities demanded by mobile systems. The first users of its 3-D super-chip concept, however, will be high-performance systems -- with the knowledge achieved there transferred to high-volume applications a few years later. In the meantime, other more economical wafer-scale techniques will be used by high-volume applications, such as its Chip on Wafer on Substrate (CoWoS) which uses TSVs to integrate multiple chips into a single super-package, such as DRAMs atop SoCs.
"We have already been working on 3-D for quite a while, and have demonstrated certain capabilities, published papers on stacking die, such as stacking DRAM die on top of logic chips and have demonstrated memory cubes, so from a technical feasibility standpoint many capabilities have already been developed," said Sun. "When it comes down to production, however, 3-D will first be used in high-end high-performance systems such as FPGAs, networking and graphic systems, which will present the entry point, along with adding more memory and other things with interposers. However, in the end 3-D must be made cost-effective if it is to be used in mobile systems. 3-D is ideal for smartphones in terms of packaging, and we have already demonstrated some design considerations, but from the production stand point it will be later. In the meantime, we have other package-on-package solutions that have already been refined for high-volume manufacturing. TSMC will have all these available, it is just a matter of which customers will be willing to pay for it, because in the end it will be the right-product, with the right-value, for the right price."
TSMC's long-term goal is to use 3-D super-chip integration to emulate the human brain, which Sun said runs on just 20-watts. To achieve that level of 3-D super-chip integration will require a 200-times shrink over today, which he estimates will be at least seven generations away, at about the 2-nanometer node circa 2028.