Minimizing system level active signal count within the memory sub-system is important for a number of reasons.
- A lower active signal count memory can often be placed in a less expensive package.
- PCB area and perhaps the number of PCB layers may be reduced when there are fewer traces to route.
- A lower active signal count memory subsystem allows the host SoC to either reallocate pins for alternate purposes or to reduce overall pin count.
- Lower active signal counts often allow memory manufacturers to test more devices simultaneously, which results in reduced testing costs.
Memory subsystem active signal count is minimized when both the volatile and non-volatile memories reside on the same bus. Consolidated busses include the Parallel NOR bus (ADP – address data parallel) and the multiplexed NOR bus (ADM – address data multiplexed). Note that the Burst ADM bus is the most attractive from a active signal count perspective (Table 1). Shared ADP/ADM NOR buses often use PSRAM devices that have a cost advantage over PC-DRAM at lower densities. At higher densities commodity PC-DRAM provide a lower cost volatile memory alternative.
PC-DRAM devices have interface characteristics that are incompatible with available non-volatile memories. If a system is to take advantage of the low cost and high performance characteristics of higher density PC-DRAM products, a split bus approach is used with independent volatile and non-volatile memory buses. This split bus approach results in a higher overall active signal count for the memory subsystem. PC-DRAM based systems use a shadowing model where the content of the non-volatile memory is copied to DRAM either during the boot process or when needed during normal operation. In these PC-DRAM based systems, execute in place functionality is not a requirement and a serial non-volatile memory interface (SPI NOR or NAND) becomes attractive from a active signal count perspective. In this split bus implementation the non-volatile SPI bus provides the lowest overall active signal count (Table 1).
TABLE 1: System Level Signal Count of Memory Combinations (Volatile + Nonvolatile)
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NOR’s system responsiveness essential in many applications
System responsiveness is largely dependent on the memory subsystem’s initial latency and bus throughput. NOR devices have significantly shorter initial access times than NAND products (Figure 3). NOR’s initial access time advantage is up to 250x when compared to SLC NAND (100ns vs. 25us) and up to 750x for MLC NAND (100ns vs. 75us). The advantage that NOR has over NAND is compounded when the virtual to physical address translation that is required in most NAND implementations is considered. In particular, the Managed NAND usage model stores the virtual to physical translation table in the NAND device and requires one or more additional read operations to identify the physical address of the desired target data. NOR based implementations often use a direct mapping of data where a virtual to physical translation is not required.
FIGURE 3: Initial Latencies
Throughput is dependent on several factors, including: how fast data can be transmitted and received on each data signal, the data bus width, and how effectively the memory device can pipeline accesses (Figure 4). PC-DRAM and LP-DRAM (LPDDRx) devices combine a low latency array structure, a high-speed signaling interface and the ability to pipeline read/write accesses. NOR devices have higher bus throughputs than legacy NAND products. While a DDR interface has been developed for NAND products, penetration into the embedded world has not yet become widespread.
NOR’s short initial latency and competitive bus rates allow for direct code execution as well as low latency data storage. This combination (low latency, high bus rates) is NOR’s fundamental technical value proposition that remains relevant, even after over 20 years of market acceptance.
FIGURE 4: Throughput on Each Data Bus Signal