The media player application, which decodes the MPEG2-TS, requires a BDA driver in the host PC to play the MPEG2-TS stream. BDA driver development is specific and customized to the MPEG2-TS source used in the design. If isochronous endpoints are used for streaming MPEG2-TS data, then the BDA driver just needs to send commands to read data from the isochronous endpoint at every polling interval. However, if an interrupt endpoint is used for reading MPEG2-TS data, then a Ping-Pong buffer mechanism needs to be implemented in the BDA driver to ensure there is no data loss in the video. If BULK endpoints are used, then there are definite chances of seeing glitches in the video output because of the bursty nature of the BULK transfers.
Figure 2. Analog PC TV Dongle
The main components are the analog TV dongle are the analog tuner, analog demodulator, CVBS to ITU656 Converter Bridge, and an USB controller. The tuner present in the TV dongle tunes the RF signal to the specific demodulator connected to it. Then the analog demodulator takes the NTSC/PAL/SECAM inputs and outputs composite video signal (CVBS) and SIF signals. The USB controller cannot pass these analog signals to the PC, so a converter chip is needed to convert the CVBS to a digitized parallel data format – ITU656. ITU656 is a parallel 8/10 bit interface for uncompressed digital video streaming. The Pixel CLK runs at 27 MHz and the active video data is given out based on the HSYNC signal (HSYNC = ‘1’) from the demodulator. The length of the video line is calculated with the help of the time-based codes: Start of Active Video (SAV) and End of Active Video (EAV). SAV and EAV are each four bytes long, where the first three bytes are FF, 00, 00 and the last byte xx is the time-based data used to calculate the length of the video line. There is a sequence of blanking data 80 10 80 10 between the EAV and SAV. The length of the blanking sequence is 280 in the case of PAL and 268 in the case of NTSC.
The length of the Active Video Line is 1440 Bytes.
Thus, the total length is 1728 for PAL (4 +1440 + 4 + 280 = 1728) and 1716 for NTSC. (4 + 1440 + 4 + 268 = 1716).
The USB controller sends this ITU656 data to the connected PC across the USB interface. Also, this USB controller needs to support an I2S interface to stream audio data to the connected PC. This USB controller enumerates as a vendor class with one Isochronous IN endpoint for video and another Isochronous IN endpoint for audio. This device is mapped to the BDA driver .sys file in the PC. The BDA driver forwards this data to the media player application where it is played.
When the user is watching a particular program on channel ‘X’ using this PC TV dongle, then there might be some other program running on another channel ‘Y’ that the user is also interested in. The user is going to miss the second program if a normal TV dongle is in use. The user experience can be enhanced by enable the dongle to demodulate two channels.
Figure 3. Block diagram of digital PC TV dongle with new feature
To achieve this, the PC TV dongle contains an extra tuner with demodulator circuitry. The user can then watch a program on channel ‘X’ with the help of digital tuner-1/demodulator-1 and the USB controller. While the user is watching channel ‘X’, the program on the channel ‘Y’ can be recorded in the background with the help of digital tuner-2/demodulator-2 and the USB controller. The challenging part in this design is that the USB controller needs to pass two MPEG2 transport streams at the same time. To support this, the USB controller enumerates with 2 Isochronous IN endpoints and the driver in the PC needs to read data from the 2 endpoints simultaneously.
Figure 4. Digital and analog PC TV dongle with USB Controller
Next-generation SuperSpeed USB 3.0 peripheral controllers enables developers to add USB 3.0 device functionality to any system. The EZ-USB FX3 shown in Figure 4. has an integrated USB 3.0 and USB 2.0 physical layer (PHYs) along with a 32-bit ARM926EJ-S microprocessor for powerful data processing and for building custom applications. It also has a fully configurable, General Programmable Interface (GPIF™ II) that can interface with the demodulator. This GPIF II supports an 8-bit, 16-bit and 32-bit parallel data bus and enables interface frequencies up to 100 MHz. The EZ-USB FX3 contains 512 KB of on-chip SRAM for code and data. It also provides interfaces to connect to serial peripherals such as UART, SPI, I2C, and I2S. The EZ-USB FX3’s internal block diagram is shown above.
In the case of a digital PC TV dongle design, the demodulator is connected to the GPIF II of FX3. The GPIF II reads the MPEG2 transport stream from the demodulator and then passes this data to the PC. I2C hardware block in the FX3 chip is used to initialize/configure the tuner and the demodulator present in this TV dongle design. To support dual channel support, the FX3 needs to be interfaced with two demodulators. Demodulator-1 is connected to the data bus and the other demodulator is connected to the address bus of FX3. FX3 can read these two MPEG2 transport streams simultaneously and passes this data to the PC connected to it over the USB interface.
The snap shot of the GPIF II designer tool is shown below. Using this flexible GPIF II designer tool, users can configure the FX3 registers to interface with any type of demodulator or with ITU656 Bridge.
Figure 5. GPIF II Designer Tool
In the case of analog PC TV dongle design, a CVBS to ITU656 chip is connected to the GPIF II of FX3. The GPIF II reads the digital data and then it passes this data to the PC. As this ITU656 runs at 27MHz, the FX3 needs to read and pass this data to PC at the rate not less than 27MBps. If this design is done with a USB2.0 controller, then the video output in the PC may not have high enough quality, as the USB interface cannot support data rates more than 24MBps with an isochronous endpoint. Thus, we need a USB3.0 controller (FX3) to match these data rate requirements. An I2S hardware block in the FX3 is used to stream audio data to the PC.
About the Author
Rama Sai Krishna. V holds an M.Tech in Systems and Control Engineering from IIT Bombay, India. He is currently working as an applications engineer on Cypress USB 2.0 peripherals.