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Speeding power estimation from weeks to hours

Gate-level waveform generation challenge
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re: Speeding power estimation from weeks to hours
WiLess   11/26/2012 7:08:36 PM
An interesting idea and really helpful. What would be the differences of this flow compared to the flow when RTL VCD along with gate-level netlist is loaded into Primetime PX and tool propagates RTL activities into gate nodes?

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re: Speeding power estimation from weeks to hours
OphirT   11/28/2012 8:00:22 AM
The first big difference is that at the end of the suggested flow you have waveform file that you can use for other needs too (and other tools too)… Also – while working with PTPX with RTL VCD you must make sure that only Flip-Flops are mapped between RTL to netlist. Usually more than Flip-Flops are mapped, and since the RTL simulation is zero delay simulation, the propagation is not done well (and the results are not accurate). It is mostly critical and problematic around adders and multipliers, but not only. The suggested flow can overcome partial design – RTL which contain stubs or other testbench that replace part of the RTL. You can’t overcome this in PTPX. In general – you must be PTPX expert to be able to run with RTL VCD, and it is not accurate. In the SpringSoft flow anyone can generate netlist VCD/SAIF, and no need to be an expert to run it on PTPX. Another issue – PTPX runs in this mode taking too much time. While generating GTL waveform in the new flow took about 1 hour, and the total power estimation was 2 hours, using this on PTPX (when it can be done) took more than 24 hours.

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